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MIC3003GFL fom management ic with internal calibration mlf and microlead frame are registered trademarks of amkor technology, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com july, 2010 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 general description the MIC3003GFL is a fiber optic module controller which enables the implementation of sophisticated, hot-pluggable fiber optic transceivers with intelligent laser control and an internally calibrated digital diagnostic monitoring interface per sff-8472. it essentially integrates all non-data path functions of an sfp/sfp+ transceiver into a tiny ( 3mm x 3mm ) mlf ? package. it also works well as a microcontroller peripheral in transponders or 10gbps transceivers. the MIC3003GFL uses the same die as the mic3003 with all its functions, but in a smaller package and different pin out. a highly configurable automatic power control (apc) circuit controls laser bias. bias and modulation are temperature compensated using dual dacs, an on-chip temperature sensor, and nvram look-up tables. a programmable internal feedback resistor provides a wide dynamic range for the apc. controlled laser turn-on. an analog-to-digital converter converts the measured temperature, voltage, bias current, transmit power, and received power from analog to digital. an eepot provides front-end adjustment of rx power. each parameter is compared against user-programmed warning and alarm thresholds. analog comparators and dacs provide fast monitoring of received power and critical laser operating parameters. data can be reported as either internally calibrated or externally calibrated. an interrupt output, power-on hour meter, and data-ready bits add user friendliness beyond sff-8472. the interrupt output and data-ready bits reduce overhead in the host system. the power-on hour meter logs operating hours using an internal real-time clock and stores the result in nvram. in addition to the features listed above, the mic3003 features an extended temperature range, options to mask alarms and warnings interrupt and txfault, a reset signal source, and the ability to support up to four chips with the same address on the serial in terface. it also supports eight- byte smbus block writes. communication with the mic3003 is via an industry standard 2-wire smbus serial interface. nonvolatile memory is provided for serial id, configuration, and separate oem and user scratchpad spaces. datasheets and support documentation can be found on micrel?s web site at: www.micrel.com . features ? packaged in a ultra small (3mm x 3mm) 24-pin mlf ? package ? extended temperature range ? alarms and warnings interrupt and txfault masks ? capability to support up to four devices on one smbus ? apc or constant-current laser bias ? turbo mode for apc loop start-up and shorter laser turn on time ? supports multiple laser types and bias circuit topologies ? integrated digital temperature sensor ? temperature compensation of modulation, bias, bias fault and alarm thresholds via nvram look-up tables ? nvram to support gbic/sfp serial id function ? user writable eeprom scratchpad ? reset signal compatible with some new systems requirements ? diagnostic monitoring interface per sff-8472 ? monitors and reports critical parameters: temperature, bias current, tx and rx optical power, and supply voltage ? s/w control and monitoring of txfault, rxlos, rateselect, and txdisable ? internal or external calibration ? eepot for adjusting rx power measurement ? power-on hour meter ? interrupt capability ? extensive test and calibration features ? 2-wire smbus-compatible serial interface ? sfp/sfp+ msa and sff-8472 compliant ? 3.0v to 3.6v power supply range ? 5v-tolerant i/o applications ? sfp/sfp+ optical transceivers ? sonet/sdh transceivers and transponders ? fibre channel transceivers ? 10gbps transceivers ? free space optical communications ? proprietary optical links
micrel, inc. MIC3003GFL july 2010 2 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 typical application ordering information part number package marking junction temp. range package type lead finish MIC3003GFL gfl 3003 with pb-free bar-line indicator ?45c to +105c 24-pin (3mm x 3mm) mlf ? pb-free, nipdau MIC3003GFLtr (1) gfl 3003 with pb-free bar-line indicator ?45c to +105c 24-pin (3mm x 3mm) mlf ? pb-free, nipdau note: 1. tape and reel.
micrel, inc. MIC3003GFL july 2010 3 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 contents general desc ription ............................................................................................................ .............................................. 1 features ....................................................................................................................... ...................................................... 1 pin confi guration .............................................................................................................. ................................................ 8 pin confi guration .............................................................................................................. ................................................ 8 pin description (m ic3003gfl only) .............................................................................................. .................................. 8 absolute maxi mum ratings ....................................................................................................... .................................... 10 operating ratings .............................................................................................................. ............................................. 10 electrical char acteristics ..................................................................................................... .......................................... 10 electrical char acteristics ..................................................................................................... .......................................... 12 electrical char acteristics ..................................................................................................... .......................................... 13 serial interface timing diagram ................................................................................................ .................................... 14 serial interfa ce addres s maps.................................................................................................. ..................................... 15 block di agram .................................................................................................................. ............................................... 18 analog-to-digital conver ter/signal m onitoring.................................................................................. .......................... 18 alarms and warnings inte rrupt source masking ................................................................................... ....................... 19 alarms and warnings as txfaul t source .......................................................................................... ....................... 21 latching of alar ms and warnings................................................................................................ ................................. 21 smbus multipar t support........................................................................................................ ...................................... 21 qgop pin f unction .............................................................................................................. ........................................ 21 calibration modes .............................................................................................................. ............................................. 22 a/ external calibra tion ........................................................................................................ .......................................... 22 voltage........................................................................................................................ ............................................ 22 temperature .................................................................................................................... ....................................... 22 bias cu rrent ................................................................................................................... ......................................... 22 tx power ....................................................................................................................... ......................................... 22 rx power....................................................................................................................... ......................................... 23 b/ internal calibration ........................................................................................................ ........................................... 23 computing internal calibration results ......................................................................................... ......................... 23 c/ reading the adc result registers............................................................................................ .............................. 25 rxpot.......................................................................................................................... ................................................ 25 laser diode bi as cont rol....................................................................................................... ....................................... 25 laser modulati on cont rol....................................................................................................... ....................................... 26 power on and las er start-up .................................................................................................... .................................. 27 fault comparators .............................................................................................................. .......................................... 28 shdn and txfin ................................................................................................................. ........................................ 29 temperature me asurement ........................................................................................................ .................................. 30 diode f aults................................................................................................................... ............................................... 30 temperature co mpensation ....................................................................................................... .................................. 30 alarms and warn ing flags ....................................................................................................... .................................... 32 control and status i/o ......................................................................................................... ......................................... 32 system timing.................................................................................................................. ............................................... 34 warm resets .................................................................................................................... ............................................ 36 power-on ho ur meter............................................................................................................ ....................................... 36 test and calibr ation features .................................................................................................. .................................... 37 serial port operation .......................................................................................................... .......................................... 38 block writes ................................................................................................................... ............................................... 38 acknowledg e polling............................................................................................................ ......................................... 39 write protection and data security ............................................................................................. ................................. 39 oem password................................................................................................................... .................................... 39 oem mode and user mode ......................................................................................................... ........................... 39 detailed register descriptions ................................................................................................. ..................................... 40 alarm threshold registers ...................................................................................................... ...................................... 40 temperature high al arm threshold ............................................................................................... .............................. 40 temperature low al arm threshold ................................................................................................ .............................. 40 voltage high alar m threshold................................................................................................... ................................... 40 d[7] read/write ............................................................................................................................... .................................... 40
micrel, inc. MIC3003GFL july 2010 4 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 d[6] read/write ............................................................................................................................... .................................... 40 voltage low alar m threshold.................................................................................................... ................................... 41 bias current high alarm threshold.............................................................................................. ................................ 41 bias current low alarm threshold............................................................................................... ................................ 41 tx optical power hi gh alarm threshold.......................................................................................... ............................ 41 tx optical power lo w alarm th reshold........................................................................................... ............................ 42 rx optical power hi gh alarm threshold .......................................................................................... ........................... 42 rx optical power lo w alarm th reshold ........................................................................................... ........................... 42 warning threshol d registers .................................................................................................... .................................... 43 temperature high wa rning threshold ............................................................................................. ............................ 43 temperature low wa rning threshold .............................................................................................. ............................ 43 voltage high warnin g threshold................................................................................................. ................................. 43 voltage low warnin g threshold.................................................................................................. ................................. 44 bias current high wa rning threshold............................................................................................ .............................. 44 bias current low wa rning threshold............................................................................................. .............................. 44 tx optical powe r high wa rning .................................................................................................. ................................. 44 tx optical powe r low warning................................................................................................... ................................. 45 rx optical power high warning threshold ........................................................................................ ......................... 45 rx optical power low warning threshold ......................................................................................... ......................... 45 checksum (chksum) checksum of bytes 0 - 94 at serial address a2h............................................................... ...... 45 adc result registers ........................................................................................................... .......................................... 46 temperatur e result ............................................................................................................. ......................................... 46 voltage........................................................................................................................ .................................................. 46 laser diode bi as cu rrent ....................................................................................................... ...................................... 46 transmitted op tical power ...................................................................................................... ..................................... 47 received opti cal power ......................................................................................................... ...................................... 47 control and stat us (cnt rl)..................................................................................................... .................................... 47 application select control m ode (ascm)......................................................................................... ............................ 48 alarm flags.................................................................................................................... .................................................. 50 alarm status regi ster 0 (alarm0) ............................................................................................... ............................... 50 alarm status regi ster 1 (alarm1) ............................................................................................... ............................... 50 warning flags.................................................................................................................. ................................................ 51 warning status r egister 0 (warn0) .............................................................................................. ............................. 51 warning status r egister 1 (warn1) .............................................................................................. ............................. 51 extended control and status (e cntrl)........................................................................................... ........................... 52 oem password en try (oempw) ..................................................................................................... ............................. 52 power-on hours (p ohh and pohl) ................................................................................................. ............................ 53 data ready flag s (data rdy) ..................................................................................................... ............................... 53 user control regi ster (usrctl) ................................................................................................. ................................ 54 resetout ....................................................................................................................... ........................................... 54 oem configuration regi ster 0 (oemcfg0) ......................................................................................... ....................... 55 oem configuration regi ster 1 (oemcfg1) ......................................................................................... ....................... 56 oem configuration regi ster 2 (oemcfg2) ......................................................................................... ....................... 57 apc setpoint 0, 1, and 2 (apcset0, apcset1, apcset2) automatic powe r control se tpoint.............................. 58 modulation setpoint 0, 1, and 2 (modset0, modset1, and modset2) nominal v mod setpoint ........................... 58 i bias fault threshold (ibflt) bias current faul t threshold.......................................................................... ............... 59 transmit power fault threshold (txflt) ......................................................................................... ........................... 59 loss-of-signal thre shold (losflt).............................................................................................. .............................. 59 fault suppression timer (flttmr) fault suppression interval in increments of 0.5 ms ........................................... 6 0 fault mask (fltmsk)............................................................................................................ ....................................... 60 oem password se tting (oempwset) ................................................................................................ ........................ 61 oem calibration 0 (oemcal0).................................................................................................... ................................ 61 oem calibration 1 (oemcal1).................................................................................................... ................................ 63 lut index (l utindx) ............................................................................................................ ...................................... 64 oem configurati on 3 (oemcfg3) .................................................................................................. ............................. 64 bias dac setting (apcdac) current vbias setting ................................................................................ ................. 65 modulation dac setting (modda c) current vm od setting........................................................................... ............ 66 oem readback regi ster (oemrd) .................................................................................................. ........................... 66
micrel, inc. MIC3003GFL july 2010 5 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 signal detect thre shold (los fltn) .............................................................................................. .............................. 67 rx eepot tap sele ction (rxpot)................................................................................................. ............................ 67 oem configurati on 4 (oemcfg4) .................................................................................................. ............................. 67 oem configurati on 5 (oemcfg5) .................................................................................................. ............................. 68 oem configurati on 6 (oemcfg6) .................................................................................................. ............................. 69 power-on hour mete r data (p ohdata) ............................................................................................. ........................ 70 oem scratchpad regi sters (scr atchn) ............................................................................................ ....................... 71 rx power coefficient look-up table (rxlutn) .................................................................................... ...................... 71 calibration consta nts (calcoefn)............................................................................................... .............................. 72 manufacturer id register (mfg _id) identifies micrel as the manufacture r of the device. always returns 2ah .......... 72 device id regi ster (dev_id) .................................................................................................... ................................... 73 package info rmation............................................................................................................ ........................................... 74
micrel, inc. MIC3003GFL july 2010 6 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 list of figures figure 1. mic3003 block diagram ................................................................................................ .................................... 18 figure 2. analog-to-digital converter blo ck diagram ............................................................................ ........................... 18 figure 3. internal calibration rx power linear a pproximation ................................................................... ..................... 25 figure 4. rxpot block diagram .................................................................................................. .................................... 25 figure 5. apc and modulation control blo ck diag ram............................................................................ ........................ 26 figure 6. programmabl e feedback resist or ....................................................................................... ............................. 26 figure 7. transmitter configurat ions supported by mic3003 ..................................................................... .................... 26 figure 8. v mod configured as voltage output with gain ....................................................................................... .......... 27 figure 9. mic3003 power- on timing (oe = 1) ..................................................................................... ........................... 28 figure 10. fault co mparator logic .............................................................................................. ..................................... 28 figure 11. satura tion detector ................................................................................................. ......................................... 29 figure 12. rxlos co mparator logic .............................................................................................. ................................. 29 figure 14. transmi tter on-off timing .......................................................................................... .................................... 34 figure 15. initialization ti ming with txdi sable asserted...................................................................... ........................ 34 figure 16. initialization timi ng with txdisable not asserted ................................................................. ..................... 34 figure 17. loss-of-s ignal (los ) timing ........................................................................................ .................................. 35 figure 19. successfully clearing a faul t condition ............................................................................ ............................. 36 figure 20. unsuccessful a ttempt to clear a fault .............................................................................. ............................. 36 figure 21. write byte protocol ................................................................................................ ......................................... 38 figure 22. read byte protocol ................................................................................................. ........................................ 38 figure 23. read_ word protocol................................................................................................. ...................................... 38 figure 24. eight-byte block write protocol.................................................................................... .................................. 39
micrel, inc. MIC3003GFL july 2010 7 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 list of tables table 1. serial interface addr ess map, device address = a0 h ........................................................................................ 15 table 2. serial interface addr ess map, device address = a2..................................................................... ..................... 15 table 3. serial interface address map (temperatu re compensation tables), device address = a4 h ............................ 16 table 4. serial interface address map (oem configuration registers), device address = a6 h ...................................... 17 table 5. a/d input signal ranges and re solutions............................................................................... ........................... 19 table 6. v aux input signal ranges and resolu tions ........................................................................................... ............. 19 table 7. alarms interrupt sources masking bits................................................................................. .............................. 20 table 8. warnings interr upt sources masking bits............................................................................... ............................ 20 table 9. resetout clear delay.................................................................................................. ................................... 21 table 10. lsb values of offset c oefficients.................................................................................... ................................. 23 table 11. internal calibration coe fficient memory map ? part i ................................................................. ...................... 24 table 12. internal calibration coe fficient memory map ? part ii ................................................................ ...................... 24 table 13. shutdown state of sh dn vs. configuration bits ....................................................................... ...................... 27 table 14. shutdown state of v bias vs. configur ation bits................................................................................................ 27 table 15. shutdown state of v mod vs. configur ation bits................................................................................................ 27 table 16. temperature com pensation look-up tables .............................................................................. ..................... 30 table 17. apc temperature co mpensation look -up table .......................................................................... ................. 31 table 18. i mod temperature compensa tion look-up table ....................................................................................... ..... 31 table 19. i bias comparator temperature co mpensation look- up table ......................................................................... 31 table 20. bias current high alar m temperature com pensation table ............................................................... ........... 31 table 21. mic3003 alar m and warni ng events..................................................................................... ........................... 33 table 22. test and diagnostic features ........................................................................................ .................................. 37
micrel, inc. MIC3003GFL july 2010 8 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 pin configuration 24-pin mlf ? (ml) pin description (MIC3003GFL only) pin number pin name pin function 1 vddd power supply input for digital functions. 2 qgpo open-drain output. can be selected (via oemcfg3 bit 7) to be an open-drain gpo or an active- low, open-drain, pulsed reset signal output controlled by the status of bits [0-2] of byte a2h: ffh. 3 gndd ground return for digital functions. 4 rs0 digital input. receiver rate select input. or?ed wi th soft rate sele ct bit srs0 to determine the state of the rrsout pin. the state of this pin is always reflected in the rs0s bit. 5 vin/int if bit 4 (ie) in the usrctl register is set to 0 (its default value), this pin is configured as an analog input. if ie bit is set to 1, this pin is configured as an open-drain output. analog input: multiplexed a/d input for monitoring su pply voltage, with a 0v to 5.5v input range. open-drain output: outputs the internally gene rated active-low interrupt signal /int. 6 clk digital input. serial clock input. 7 data digital i/o, open-drain, bi-dir ectional serial data input/output. 8 txdisable digital input; active high. the transmitter is disabled when this input is high or the stxdis bit is set to 1. the state of this input is always reflected in the txdis bit. 9 txfault digital output; open-drain, with programmable polar ity. if oemcfg5 bit 4 is set to 0, a high level indicates a hardware fault impeding transmitter operation. if oemcfg5 bit 4 is set to 1, a low level indicates a hardware fault impeding transmitter operat ion. the state of this pin is always reflected in the txflt bit. 10 rs1 digital input; transmitter rate sele ct input; or?ed with soft rate se lect bit srs1 to determine the state of the trsout pin. the state of this pin is always reflected in the rs1s bit. 11 vrx analog input. multiplexed a/d converter input for monitoring received optical power. the input range is 0 to v ref . a 5-bit programmable eepot on this pin provides coarse calibration and ranging of the rx power measurement.
micrel, inc. MIC3003GFL july 2010 9 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 pin number pin name pin function 12 shdn/txfin digital output/input; programmable polarity. w hen used as shutdown output (shdn), oemcfg3 bit 2 set to 0, shdn is asserted at the detection of a fault condition if oemcfg4 bit 7 is set to 0. if oemcfg4 bit 7 is set to 1, a fault condition wi ll not assert shdn. when programmed as txfin, it is an input for external fault signals to be or?ed wi th the internal fault sources to drive txfault. 13 vild+ analog input. multiplexed a/d input for monitoring laser bias current via a sense resistor (signal input); accommodates inputs referenced to v dd or gnd (see pin 14 description). 14 vild? analog input. reference terminal for the multiple xed pseudo-differential a/d converter inputs for monitoring laser bias current via a sense resistor (vild+ is the sensing input). tie to v dd or gnd to reference the voltage sensed on vild+ to v dd or gnd, respectively. 15 vdda power supply input for analog functions. 16 gnda ground return for analog functions. 17 vmpd analog input. multiplexed a/d converter input fo r monitoring transmitted optical power via a monitor photodiode. in most applications, vmpd will be connected directly to fb. the input range is 0 - v ref or 0 - v ref /4 depending upon the setting of the apc configuration bits 18 fb analog input. feedback voltage for the apc loop op-amp. polarity and scale are programmable via the apc configuration bits i oemcfg1. connect to v bias if apc is not used. 19 vmod analog output. buffered dac output to set the modulation current on the laser driver ic. operates with either a 0? v ref or a (v dd ?v ref ) ? v dd output swing so as to generate either a ground- referenced or a v dd referenced programmed voltage. a simple external circuit can be used to generate a programmable current for those driver s that require a current rather than a voltage input. 20 vmod? analog input. this pin is the inverting terminal of the vmod buffer op-amp. connect to vmod (gain = 1) or a feedback resistor network to set a different gain value. 21 vbias analog output. buffered dac output capable of sour cing or sinking up to 10ma under control of the apc function to drive an external transistor or the apcset pin of a laser diode driver for laser diode dc bias. the output and feedback polari ty are programmable to accommodate either an npn or a pnp transistor to drive a common-anode or common-cathode laser diode. 22 comp analog output. compensation terminal for the apc loop. connect a capacitor between this pin and gnda or v dda with the appropriate value to tune the apc loop time constant to a desirable value. 23 rrsout/ gpo digital output. open-drain or push-pull. if oemcfg3 bit 4 is set to 0, rrsout is selected. it represents the receiver rate select as per sff. this output is controlled by the srs0 bit or?ed with rs0 input and is open drain only. if oemcfg3 bit 4 is set to 1, gpo is selected. general-purpose, non-volatile output, it is controlled by the gpo configuration bits in oemcfg3. 24 rxlos/ trsout digital output. this programmable polarit y, open-drain outputs has two purposes: if oemcfg6 bit 2 = 0, indicates the loss of the rece ived signal as indicated by a level of received optical power below the programmed rxlos com parator threshold; may be wire-or?ed with external signals. normal operation is indicated by a low level when oemcfg6 bit 3 is set to 0 and a high level when oemcfg6 bit 3 is set to 1. rxlos is de-asserted when vrx > losfltn. the los bit reflects the state of rxlos whether driven by the mic3003 or an external circuit. if oemcfg6 bit 2 = 1, trsout is selected. this signal represents the transmitter rate select as per the sff specification. this output is controlled by the srs1 bit or?ed with the rs1 input.
micrel, inc. MIC3003GFL july 2010 10 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 absolute maximum ratings (1) power supply voltage, v dd ....................................... +3.8v voltage on clk, data, txfault, vin, rxlos, txdisable, rs0, rs1 ......................... ?0.3v to +6.0v voltage on any other pin.....................?0.3v to v dd +0.3v power dissipation, t a = 85c .................................... 1.5w junction temperature (t j ) ....................................... 150c storage temperature (t s )....................... ?65c to +150c soldering (20 sec.) ................................................... 260o c esd ratings (3) human body model.................................................. 2kv machine mode l ....................................................... 300v operating ratings (2) power supply voltage, v dda /v ddd ........... +3.0v to +3.6v ambient temperature range (t a ) .......?40c to +105c package thermal resistance mlf ? ( ja ) .................................................60c/w electrical characteristics for typical values, t a = 25c, v dda = v ddd = +3.3v, unless otherwise noted. bold values are guaranteed for +3.0v (v dda = v ddd ) 3.6v, t (min) t a t (min) , (8) symbol parameter condition min typ max units power supply clk = data = v ddd = v dda ; txdisable low; all dacs at full-scale; all a/d inputs at full-scale; all other pins open. 2.3 3.5 ma i dd supply current clk = data = v ddd = v dda ; txdisable high; fltdac at full-scale; all a/d inputs at full-scale; all other pins open. 2.3 3.5 ma v por power-on reset voltage all registers reset to default values; a/d conversions initiated. 2.9 2.98 v v uvlo under-voltage lockout threshold note 5 2.5 2.73 v v hyst power-on reset hysteresis voltage 170 mv t por power-on reset time v dd > v por, note 4 50 s v ref reference voltage 1.210 1.225 1.240 v v ref / v dda voltage reference line regulation 1.7 mv/v temperature-to-digital converter characteristics local temperature measurement error ?40c t a +105c, note 6 1 3 c t conv conversion time note 4 60 ms t sample sample period 100 ms voltage-to-digital converter characteristics (v rx , v aux , v bias , v mpd , v ild ) voltage measurement error ?40c t a +105c, note 6 1 2.0 %fs t conv conversion time note 4 10 ms t sample sample period note 4 100 ms notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. devices are esd sensitive. handli ng precautions recommended. human body mo del, 1.5k in series with 100pf. 4. guaranteed by design and/or testing of related parameters. not 100% tested in production. 5. the mic3003 will attempt to enter its shutdown state when v dd falls below v uvlo . this operation requires time to complete. if the supply voltage falls too rapidly, the operation may not be completed. 6. does not include quantization error.
micrel, inc. MIC3003GFL july 2010 11 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 voltage input, v in (pin 5 used as an adc input) symbol parameter condition min typ max units v in input voltage range ?0.3 v v dd 3.6v gnda 5.5 v i leak input current v in = v dd or gnd; v aux = v in 55 a c in input capacitance 10 pf digital-to-voltage converter characteristics (v mod , v bias ) accuracy ?40c t a +105c, note 7 1 2.0 %fs t conv conversion time note 8 20 ms dnl differential non-linearity error note 8 0.5 1 lsb bias current sense inputs, v ild +, v ild ? v ild differential input signal range, | v ild + ? v ild ? | 0 v ref /4 mv i in+ v ild + input current 1 a v ild ? referred to v dda +150 a i in? v ild ? input current | v ild + ? v ild ? | = 0.3v v ild ? referred to gnd -150 a c in input capacitance 10 pf apc op amp, fb, v bias , comp gbw gain bandwidth product c comp = 20pf; gain = 1 1 mhz tc vos input offset voltage temperature coefficient (4) 1 v/c i out = 10ma, srce bit = 1 gnda 1.25 v v out output voltage swing i out = -10ma, srce bit = 0 v dda -1.25 v dda v i sc output short-circuit current 55 ma t sc short circuit withstand time t j 150c, note 8 sec c comp = 20pf; gain = 1, to gnd 55 db psrr power supply rejection ratio c comp = 20pf; gain = 1, to v dd 40 a min minimum stable gain c comp = 20pf, note 8 1 v/v v/ t slew rate c comp = 20pf; gain = 1 3 v/s rfb internal feedback resistor tolerance 20 % rfb/ t internal feedback resistor temperature coefficient 25 ppm/c start = 01 h 0.375 ma start = 02 h 0.750 ma start = 04 h 1.500 ma i start laser start-up current magnitude start = 08 h 3.000 ma c in pin capacitance 10 pf notes: 7. does not include quantization error. 8. guaranteed by design and/or testing of related parameters. not 100% tested in production.
micrel, inc. MIC3003GFL july 2010 12 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 electrical characteristics symbol parameter condition min typ max units v mod buffer op-amp, vmod, v mod ? gbw gain bandwidth c comp = 20pf; gain = 1 1 mhz tc vos input offset voltage temperature coefficient 1 v/c i bias v mod ? input current 0.1 1 a v out output voltage swing i out = 1ma gnda+75 v dda -75 mv i sc output short-circuit current 35 ma t sc short circuit withstand time t j 150c, note 9 sec c comp = 20pf; gain = 1, to gnd 65 db psrr power supply rejection ratio c comp = 20pf; gain = 1, to v dd 44 db a min minimum stable gain c comp = 20pf 1 v/v v/ t slew rate c comp = 20pf; gain = 1 1 v/s c in pin capacitance 10 pf control and status i/o, txdisable, txfault, rs0, rrsout(gpo), shdn(txfi n), rxlos(trsout), /int, rs1, qgpo v il low input voltage 0.8 v v ih high input voltage 2.0 v v ol low output voltage i ol 3ma 0.3 v v oh high output voltage (applies to shdn only) i oh 3ma v ddd ?0.3 v i leak input current 1 a c in input capacitance 10 pf transmit optical power input, v mpd v in input voltage range note 9 gnda v dda v biasref=0 v ref v v rx input signal range biasref=1 v dda ?v ref v dda v c in input capacitance note 9 10 pf i leak input current 1 a received optical power input, vrx, rxpot input voltage range note 9 gnda v dda v v rx valid input signal range (adc input range) 0 v ref v r rxpot(32) end-to-end resistance rxpot = 1f h 32 k ? rxpot resistor tolerance 20 % rxpot/ t resistor temperature coefficient 25 ppm/oc v rx /v rxpot divider ratio accuracy 00 rxpot 1f h -5 +5 % i leak input current rxpot = 0 (d isconnected) 1 a c in input capacitance note 9 10 pf i leak input current 1 a note: 9. guaranteed by design and/or testing of related parameters. not 100% tested in production.
micrel, inc. MIC3003GFL july 2010 13 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 electrical characteristics symbol parameter condition min typ max units control and status i/o timing, txfault, txdisable, rs0, rrsout, and rxlos t off txdisable assert time from i nput asserted to optical output at 10% of nominal, c comp = 10nf. 10 s t on txdisable de-assert time from input de-asserted to optical output at 90% of nominal, c comp = 10nf. 1 ms t init initialization time from power on or transmitter enabled to optical output at 90% of nominal and tx_fault de-asserted. note 10. 300 ms t init2 power-on initialization time from power on to apc loop-enabled. 200 ms t fault txfault assert time from fault condition to txfault assertion. note 10. 95 s t reset fault reset time length of time txdisable must be asserted to reset fault condition. 10 s t loss_on rxlos assert time from loss of signal to rxlos asserted. 95 s t loss_off rxlos de-assert time from signal acquisition to los de-asserted. 100 s t data analog parameter data ready from power on to valid analog parameter data available. note 10 400 ms t prop_in txfault, txdisable, rxlos, rs0, rs1 input propagation time time from input change to corresponding internal register bit set or cleared. note 10. 1 s t prop_out txfault, trsout, trrsout, /int, qgpo output propagation time from an internal register bit set or cleared to corresponding output change. note 10. 1 s fault comparators flttmr fault suppression timer clock period note 10. 0.475 0.5 0.525 ms accuracy -3 +3 %/fs t reject glitch rejection maximum length pulse that will not cause output to change state. note 10. 4.5 s high level 95 %vdda v sat saturation detection threshold low level 5 %vdda power-on hour meter timebase accuracy 0c t a +70, note 10. +5 -5 % ?40c t a +105c +10 -10 % resolution note 10. 10 hours non-volatile (flash) memory t wr write cycle time, note 11 measured from the smbus stop condition of a one-byte to eight-byte write transaction. note 10. 13 ms nvram data retention 100 years endurance maximum permitted number of write cycles to any single nvram location 10,000 cycles notes: 10. guaranteed by design and/or testing of related parameters. not 100% tested in production. 11. the mic3003 will not respond to serial bus transactions during an eeprom write cycl e. the host will receive a nack response during t wr .
micrel, inc. MIC3003GFL july 2010 14 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 serial data i/o pin, data symbol parameter condition min typ max units i ol = 3ma 0.4 v v ol low output voltage i ol = 6ma 0.6 v v il low input voltage 0.8 v v ih high input voltage 2.1 v i leak input current 1 a c in input capacitance note 12 10 pf serial clock input, clk v il low input voltage 2.7v v dd 3.6v 0.8 v v ih high input voltage 2.7v v dd 3.6v 2.1 v i leak input current 1 a c in input capacitance note 12 10 pf serial interface timing (4) t 1 clk (clock) period 2.5 s t 2 data in setup time to clk high 100 ns t 3 data out stable after clk low 300 ns t 4 data low setup time to clk low start condition 100 ns t 5 data high hold time after clk high stop condition 100 ns t data data ready time from power on to completion of one set of adc conversions; analog data available via serial interface. 400 ms qgpo reset pulse timing t 1 qgpo reset pulse low duration oemcfg3 bit 7 = 1 a2h:255 (ffh) [2-0] switch to 111 112.5 125 137.5 s t 2 qgpo reset de-assertion to the clearing of a2:ffh bits 2:0 oemcfg3 bit 7 = 1 a2h:255 (ffh) [2-0] 111 20.25 22.5 24.75 ms note: 12. guaranteed by design and/or testing of related parameters. not 100% tested in production. serial interface timing diagram serial interface timing
micrel, inc. MIC3003GFL july 2010 15 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 serial interface address maps address (decimal) field size (bytes) name description 0 ?95 96 serial id defined by sfp msa general- purpose nvram; r/w under valid oem password. 96 ? 127 32 vendor specific vendor specific eeprom 128 ? 255 128 reserved reserved for future use. general-purpose nvram; r/w under valid oem password. table 1. serial interface address map, device address = a0 h address(s) hex dec field size (bytes) name description 00-27 0-39 40 alarm and warning thresholds high/low limits for warnings and alarms; writeable using the oem password; read-only otherwise. 28-37 40-55 16 reserved reserved ? do not write; reads undefined. 38-5b 56-91 36 calibration constants numerical cons tants for external calibration; writeable using the oem password; read-only otherwise. 5c-5e 92-94 3 reserved reserved ? do not write; reads undefined. 5f 95 1 checksum general-purpose nvra m; writeable using the oem password; read-only otherwise. 60-69 96-105 10 analog data real time analog parameter data. 6a-6d 106-109 4 reserved reserved ? do not write; reads undefined. 6e 110 1 control/status regist er control and status bits. 6f 111 1 rate select control bits [7-6] cont rol the use of the rs0 and rs1 inputs and the srs0 and srs1 register bits. 70-71 112-113 2 alarm flags alarm status bits; read-only. 72-73 114-115 2 reserved reserved ? do not write; reads undefined. 74-75 116-117 2 warning flags warning status bits; read-only. 76 118 1 extended control/status register additional control and status bits. 77 119 1 reserved reserved ? do not write; reads undefined. 78-7e 120-126 7 oempw oem password entry field. the four-byte oem password location can be selected to be 78h-7bh (120-123) by setting oemcfg5 bit 2 to 0 (default) or 7bh-7eh (123-126) by setting oemcfg5 bit 2 to a one. 7f 127 1 vendor-specific vendor specific. reserved ? do not write; reads undefined. 80-f7 128-247 120 user scratchpad user-wri teable eeprom. general-purpose nvram. f8-f9 248-249 2 alarms masks bit = 0: corresponding alarm not masked. bit = 1: corresponding alarm masked. fa-fb 250-251 2 warnings masks bit = 0: corresponding warning not masked. bit = 1: corresponding warning masked. fc-fd 252-253 2 reserved reserved ? do not write; reads undefined. fe 254 1 usrctl end-user control and status bits. ff 255 1 resetout bits [2:0] of this regist er control the qgpo reset output (pin 2) if oemcfg3 bit 7 is set to 1. table 2. serial interface address map, device address = a2
micrel, inc. MIC3003GFL july 2010 16 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 address(s) hex dec field size (bytes) name description 00-3f 0-63 64 biaslut1 first 64 entries of the bias current temperature compensation lut (look- up table) the additional 12 entries are located in a6: 58h ? 63h. 40-7f 64-127 64 modlut1 first 64 entries of the modulation current temperature compensation lut. the additional 12 entries are located in a6:.64h ? 6fh. 80-bf 128-191 64 iftlut1 first 64 entries of the bias curr ent fault threshold temperature compensation lut. the additional 12 entries are located in a6: 70h - 7bh. c0-ff 192-255 64 hatlut1 first 64 entries of the bias current high alarm threshold temperature compensation lut. the additional 12 entries are located in a6: 7c-87h. table 3. serial interface address map (temperature compensation tables), device address = a4 h address(s) hex dec field size (bytes) name description 00 0 1 oemcfg0 oem configuration register 0 01 1 1 oemcfg1 oem configuration register 1 02 2 1 oemcfg2 oem configuration register 2 03 3 1 apcset0 apc setpoint register 0 04 4 1 apcset1 apc setpoint register 1 05 5 1 apcset2 apc setpoint register 2 06 6 1 modset0 modulation setpoint register 0 07 7 1 ibflt bias current fault-comparator thresh old. this register is temperature compensated. 08 8 1 txpflt tx power fault threshold 09 9 1 losflt rx los fault-comparator threshold 0a 10 1 flttmr fault comparator timer setting 0b 11 1 fltmsk fault source mask bits 0c-0f 12-15 4 oempwset password for access to oem areas 10 16 1 oemcal0 oem calibration register 0 11 17 1 oemcal1 oem calibration register 1 12 18 1 lutindx look-up table index read-back 13 19 1 oemcfg3 oem configuration register 3 14 20 1 apcdac reads back current apc dac value (setpoint+offset) 15 21 1 moddac reads back current modu lation dac value (setpoint+offset) 16 22 1 oemread reads back oem calibration data 17 23 1 losfltn los de-assert threshold 18 24 1 rxpot rxpot tap selection 19 25 1 oemcfg4 oem configuration register 4 1a 26 1 oemcfg5 oem configuration register 5 1b 27 1 oemcfg6 oem configuration register 6 1c-1d 28-29 2 scratch reserved ? do not write; reads undefined. 1e 30 1 modset 1 modulation setpoint register 1
micrel, inc. MIC3003GFL july 2010 17 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 address(s) hex dec field size (bytes) name description 1f 31 1 modset 2 modulation setpoint register 2 20-27 32-39 8 pohdata power-on hour meter scratchpad 28-47 40-71 32 rxlut rx power internal calibration coeffi cient table. eight sets of slope and offset coefficients provide a piecewise-linear transform for the receive power adc result. 48-57 72-87 16 calcoef slope and offset coefficients used for temperature, voltage, bias current, and transmit power internal calibration 58-63 88-99 12 iftlut2 additional 12 entries of the bias cu rrent fault threshold temperature compensation lut. 64-6f 100-111 12 biaslut2 additional 12 entries of t he bias current temperature compensation lut. 70-7b 112-123 12 modlut2 additional 12 entries of the m odulation current temperature compensation lut. 7c-87 124-135 12 hatlut2 additional 12 entries of the bias current high alarm threshold temperature compensation lut. 88-cf 136-207 72 scratch oem scratchpad area d0-dd 208-221 14 rxlutseg/ scratch receive power calibration segment delimiters. each of the eight segments can have its own slope and offset coefficient. used to refine the shape of the piecewise-linear f unction used for receive power in internal calibration mode. these bytes may also be part of the oem scratch pad if the hard coded delimiters option is selected, see the description of oemcfg6 de-fa 222-250 29 scratch oem scratchpad area fb-fc 251-252 2 poh power on hour meter result; read-only fd 253 1 data ready flags data ready bits for each measured parameter; read-only fe 254 1 mfg_id manufacturer identification (micrel?s manufacturer id is 42, 2ah) ff 255 1 dev_id device id and die revision table 4. serial interface address map (oem configuration registers), device address = a6 h
micrel, inc. MIC3003GFL july 2010 18 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 block diagram figure 1. mic3003 block diagram analog-to-digital converter/signal monitoring a block diagram of the monitoring circuit is shown below. each of the five analog parameters monitored by the mic3003 is sampled in sequence. all five parameters are sampled and the results updated within the t conv duration given in the ?electrical charac teristics? section. in oem mode, the channel that is normally used to measure v in may be assigned to measure the level of the v dda pin or one of five other nodes. this provides a kind of analog loopback for debug and test purposes. the v aux bits in oemcfg0 control which voltage source is being sampled. the various v aux channels are level-shifted differently depending on the signal source, resulting in different lsb values and signal ranges. see table 5. figure 2. analog-to-digital converter block diagram
micrel, inc. MIC3003GFL july 2010 19 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 channel adc resolution (bits) conditions input range (v) lsb (1) temp 8 or 9 n/a 1c or 0.5c vaux 8 see table 6 gain = 0; biasref = 0 gnda - v ref gain = 0; biasref = 1 v dda ? (v dda ? v ref ) 4.77mv gain = 1; biasref = 0 gnda - v ref /4 vmpd 8 gain = 1; biasref = 1 v dda ? (v dda ? v ref /4) 1.17mv vild- = vdda v dda ? (v dda ? v ref ) vild 8 vild- = gnda gnda - v ref 4.77mv vrx 12 rxpot = 00 0 - v ref 0.298mv table 5. a/d input signal ranges and resolutions note: 1. assumes typical vref value of 1.22v. channel vaux [2:0] input range (v) lsb (1) (mv) v in 000 = 00 h 0.5v to 5.5v 25.6mv v dda 001 = 01 h 0.5v to 5.5v 25.6mv v bias 010 = 02 h 0.5v to 5.5v 25.6mv v mod 011 = 03 h 0.5v to 5.5v 25.6mv apcdac 100 = 04 h 0v to v ref 4.77mv moddac 101 = 05 h 0v to v ref 4.77mv fltdac 110 = 06 h 0v to v ref 4.77mv table 6. v aux input signal ranges and resolutions note: 1. assumes typical v ref value of 1.22v. alarms and warnings interrupt source masking alarm and warning violations set the flags in the alarm and warning status register s, and also assert the interrupt output if they are not masked. if an alarm or warning is masked, it will not set the interrupt. table 8 shows the locations of the masking bits. the warning or alarm is masked if the corresponding bit is set to 1.
micrel, inc. MIC3003GFL july 2010 20 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 serial address a2h byte bit default value description 7 0 masking bit for temperature high alarm interrupt source 6 0 masking bit for temperature low alarm interrupt source 5 0 masking bit for voltage high alarm interrupt source 4 0 masking bit for voltage low alarm interrupt source 3 0 masking bit for bias high alarm interrupt source 2 0 masking bit for bias low alarm interrupt source 1 0 masking bit for tx power high alarm interrupt source 248 0 0 masking bit for tx power low alarm interrupt source 7 0 masking bit for rx power high alarm interrupt source 6 1 masking bit for rx power low alarm interrupt source 249 [5-0] reserved table 7. alarms interrupt sources masking bits serial address a2h byte bit default value description 7 0 masking bit for temperature high warning interrupt source 6 0 masking bit for temperature low warning interrupt source 5 0 masking bit for voltage high warning interrupt source 4 0 masking bit for voltage low warning interrupt source 3 0 masking bit for bias high warning interrupt source 2 0 masking bit for bias low warning interrupt source 1 0 masking bit for tx power high warning interrupt source 250 0 0 masking bit for tx power low warning interrupt source 7 0 masking bit for rx power high warning interrupt source 6 1 masking bit for rx power low warning interrupt source 251 [5-0] reserved table 8. warnings interrupt sources masking bits
micrel, inc. MIC3003GFL july 2010 21 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 alarms and warnings as txfault source alarms and warnings are not sources for txfault with the default setting. to set alarms as a txfault source set oemcfg4 bit 6 to 1. to set warnings as a txfault, source set oemcfg4 bit 7 to 1. the alarms and warnings txfault sources can be masked individually in the same way shown in tables 7 and 8. latching of alarms and warnings alarms and warnings are latched by default, i.e., once asserted the flags remain on until the register is read or txdsable is toggled. if oemcfg4 bit 5 is set to 1, the warnings are not latched and will be set and reset with the warning condition. reading the register or toggling txdisable will clear the flag. if oemcfg4 bit 4 is set to 1, the alarms are not latched and will be set and reset with the alarm condition. read ing the register or toggling txdisable will clear the flag. smbus multipart support if more than one MIC3003GFL device shares the same serial interface and multipart mode is selected on them (oemcfg5 bit 3 = 1), then pin 12 and pin 23 become smbus address bits 3 and 4 respectively. therefore, the parts should have a different setting on those pins to create four address combinations based upon the state of pin 12 and pin 23 state, (00, 01, 10, 11) where 0 is a pull down to gnd and 1 is a pull up to vcc. the parts come from the factory with the same address (a0) and multipart mode off (oemcfg5 bit 3 is 0). after power up, write 1 to oemcfg5 bit 3 to turn on multipart mode, which is done to all parts at the same time since they all respond to serial address a0 at this point. with multipart mode on, the parts have now different addresses based on the states of pins 12 and 23. another option is to access each part individually, set their single mode address in oemcfg2 bits [4-7] to different values and then turn off multipart mode to return to normal mode where the parts have new different addresses. qgop pin function qgop can be used in gop mode as a general purpose output by setting oemcfg3 bit 7 to 0, or as in reset mode as a reset signal output by setting oemcfg3 bit 7 to 1. if reset mode is selected, t he reset signal state is controlled by rsetout (a2:ffh bits [2-0]). by default, these three bits are 000, and the qgpo output is undriven (state: high). when the three bits are written to 111, qgpo?s open-drain output will be driven low for 125 s (typical), after which qgpo reenters the undriven state. the resetout field is cleared from 111 to 000 22.5 ms (typical) after the de-assertion edge of qgpo. other values of this delay may be selected by setting trstclr (oemcfg2 bits [2-0]) to different values as shown on table. if reset mode in oemcfg3 is not selected, these three bits have no function. trstclr [2-0] delay from qgpo switching high to resetout clear 000 zero delay 001 17.5 ms typical 010 22.5 ms typical (default) 011 27 ms typical 100 45 ms typical table 9. resetout clear delay
micrel, inc. MIC3003GFL july 2010 22 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 calibration modes the default mode of calibration in the mic3003 is external calibration, for which the intcal bit (bit 0 in oemcfg3 register) is set to 0. the internal calibration mode is selected by setting intcal to 1. a/ external calibration the voltage and temperature values returned by the mic3003?s a/d converter are internally calibrated. the binary values of temph:templ and volth:voltl are in the format called for by sff-8472 under internal calibration. sff-8472 calls for a set of calibration constants to be stored by the transceiver oem at specific non-volatile memory locations; refer to the sff-8472 specifications for the memory map of the calibration coefficients. the mic3003 provides the non-volatile memory required for the storage of these constant s. the digital diagnostic monitoring interface specification should be consulted for full details. slopes and offsets are stored for use with voltage, temperature, bias current, and transmitted power measurements. coeffi cients for a fourth-order polynomial are provided for use with received power measurements. the host sy stem can retrieve these constants and use them to process the measured data. voltage the voltage values returned by the mic3003?s a/d converter are internally calibrated. the binary values of volth:voltl are in the format called for by sff-8472 under internal calibration. since vinh:vinl requires no processing, the corresponding slope should be set to one and the offset to zero. temperature the temperature values returned by the mic3003?s a/d converter are internally calibrated. the binary values of temph:templ are in the format called for by sff-8472 under internal calibration. the temperature value may be offset by storing a value in a6:74(4ah). the temperature offset is a six-bit signed quantity with .5 degrees c resolution. the temperature offset coefficient at a6:74(4ah) is used in the same way in both internal and external calibration modes. bias current bias current is sensed via an external sense resistor as a voltage appearing between vild+ and vild-. the value returned by the a/d is therefore a voltage analogous to bias current. bias current, ibias, is simply v vild /r sense . the binary value in ibiash (ibiasl is always zero) is related to bias current by: () sense bias r 255 ibiash v 3 . 0 = i (1) the value of the least significant bit (lsb) of ibiash is given by: sense sense r 255 mv 300 = amps r 255 v 3 . 0 = ) ibiash ( lsb a r 9 . 1176 = ma sense (2) per sff-8472, the value of the bias current lsb is 2a. the necessary conversion factor , ?slope?, is therefore: sense sense r + 298 . 2 = r a 512 a 5 . 1176 = slope the tolerance of the sense re sistor directly impacts the accuracy of the bias current measurement. it is recommended that the sense resistor chosen be 1% accurate or better. the offset correction, if needed, can be determined by shutting down the laser, i.e., asserting txdisable, and measuring the bias current. any non- zero result gives the offset required. the offset will be equal and opposite to the result of the ?zero current? measurement. tx power transmit power is sensed via a resistor carrying the monitor photodiode current. in most applications, the signal at vmpd will be feedback voltage on fb. the vmpd voltage may be measured relative to gnd or v dda depending on the setting of the biasref bit in oemcfg1. the value returned by the a/d is therefore a voltage analogous to transmit power. the binary value in txoph (txopl is always zero) is related to transmit power by: () sense sense r 255 txoph mv 1220 k = r 255 txoph vref k = ) mw ( ptx mw r txoph 7843 . 4 k = sense (3) for a given implementation, the value of r sense is known. it is either the value of the external resistor or the selected internal value of r fb . the constant, k, will likely have to be determined through experimentation or closed-loop calibration, as it depends on the monitoring photodiode responsively and coupling efficiency. it should be noted that the apc circuit acts to hold the transmitted power constant. the value of transmit power reported by the circuit should only vary by a small amount as long as the apc is functioning correctly.
micrel, inc. MIC3003GFL july 2010 23 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 rx power received power is sensed as a voltage appearing at vrx. it is assumed that this voltage is generated by a sense resistor carrying the receiver photodiode current or by the rssi circuit of the receiver. the value returned by the a/d is therefore a voltage analogous to received power. the binary values in rxoph and rxopl are related to receive power by: () 65536 ? 16 / rxopl + rxoph 256 vref k = ) mw ( rx (4) for a given implementation, the constant, k, will likely have to be determined through experimentation or closed-loop calibration, as it depends upon the gain and efficiencies of the receiver. in sff-8472 implementations, the external calibration constants can describe up to a fourth-order polynomial in case k is nonlinear. b/ internal calibration if the intcal bit in oemcfg3 is set to 1 (internal calibration selected), the mic3003 will process each piece of data coming out of the a/d converter before storing the result in result register. linear slope/offset correction will be applied on a per-channel basis to the measured values for voltage, bias current, tx power, and rx power. only offset is applied to temperature. the user must store the appropriate slope/offset coefficients in memory at the time of transceiver calibration. in the case of rx power, a look-up table is provided that implements eight-segment piecewise- linear correction. this correction may be performed as a compensation of the receiver non-linearity over temperature or receive power level. if static slope/offset correction for rx power is desired, the eight coefficient sets can simply be made the same. the user has the option to select between using preset hard-coded delimiters values or prog rammable delimiters where delimiters corresponding to the best linear approximation intervals of a specific receiver can be entered. the latter option will use an additional fourteen (14) bytes from the oem scratch pad a6h:208-221(do h -dd h ). oemcfg6 bits [6:5] are used to select between these options. the memory maps for the calibration coefficients are shown in tables 11 and 12. if the programmable delimiters option is selected, the user must enter the seven delimiters of the intervals t hat best fit the receiver response. the diagram in figure 3 shows the link between the delimiters and the sets of slopes and offsets. slopes coefficients the slopes allow for the correction of gain errors. each slope coefficient is an unsigned, sixteen-bit, fixed-point binary number in the format: [] llllllll . mmmmmmmm (5) where m is a data bit in the most-significant byte and l is a data bit in the least significant byte slopes are always positive. the decimal point is in between the two bytes, i.e., between bits 7 and 8. this provides a numerical range of 1/256 (0.00391) to 255.997 in steps of 1/256. t he most significant byte is always stored in memory at the lower numerical address. offset coefficients the offsets correct for const ant errors in the measured data. each offset, apart from temperature, is a signed, sixteen-bit, fixed-point binary number. the bit-weights of the offsets are the same as t hat of the final results. the sixteen-bit offsets provide a numerical range of ?32768 to +32767 for voltage, bias current, transmit power, and receive power. the numerical range for the six-bit temperature offset is ?32 (?16 c) to +31 (+15.5 c) in increments of .5 c. the two most significant bits of the temperature offset coefficient are ignored by the mic3003. computing internal calibration results calibration of voltage, bias current, and tx power are performed using the following calculation: offsetn + slopen resultn _ adc = resultn (6) calibration of rx power is performed using the following calculation: ) m ( offset + ) m ( slope result _ adc = result (7) where m represents one of the eight linearization intervals corresponding to the rx power level. the results of these calculat ions are rounded to sixteen bits. if the seventeenth bit is a one, the result is rounded up to the next higher value. if the seventeenth bit is zero, the upper sixteen bits remain unchanged. the bit- weights of the offsets are the same as that of the final results. for sff-8472 compatible applications, these bit- weights are given in table 10. parameter magnitude of lsb voltage 100v bias current 2a tx power 0.1w rx power 0.1w table 10. lsb values of offset coefficients
micrel, inc. MIC3003GFL july 2010 24 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 address(s) hex dec field size name description 48-49 72-73 2 reserved reserved. there is no slope for temperature. do not write; reads undefined. 4a-4b 74-75 2 toffh:toffl temperature offset; signed six-bit integer offset with an lsb resolution of .5 degrees c per bit. the two most significant bits of toffh are ignored. toffl is not used. note that toffh is also used in external calibration mode. 4c-4d 76-77 2 vslph:vslpl voltage slope; unsigned fixed-point; msb is at lower physical address. 4e-4f 78-79 2 voffh:voffl voltage offset; signed integer; msb is at lower physical address. 50-51 80-81 2 islph:islpl bias current slope; unsign ed fixed-point; msb is at lower physical address. 52-53 82-83 2 ioffh:ioffl bias current offset; signed integer; msb is at lower physical address. 54-55 84-85 2 txslph: xslpl tx power slope; unsigned fixed-point; msb is at lower physical address. 56-57 86-87 2 txoffh: txoffl tx power slope; unsig ned fixed-point; msb is at lower physical address. table 11. internal calibration coefficient memory map ? part i address(s) hex dec field size name description 28-29 40-41 2 rxslp0h: rxslp0l rx power slope 0; uns igned fixed-point; msb is at lower physical address. 2a-2b 42-43 2 rxoff0h: rxoff0l rx power offset 0; signed integer; msb is at lower physical address. 2c-2d 44-45 2 rxslp1h: rxslp1l rx power slope 1; uns igned fixed-point; msb is at lower physical address. 2e-2f 46-47 2 rxoff1h: rxoff1l rx power offset 1; signed integer; msb is at lower physical address. 30-31 48-49 2 rxslp2h: rxslp2l rx power slope 2; uns igned fixed-point; msb is at lower physical address. 32-33 50-51 2 rxoff2h: rxoff2l rx power offset 2; signed integer; msb is at lower physical address. 34-35 52-53 2 rxslp3h: rxslp3l rx power slope 3; uns igned fixed-point; msb is at lower physical address. 36-37 54-55 2 rxoff3h: rxoff3l rx power offset 3; signed integer; msb is at lower physical address. 38-39 56-57 2 rxslp4h: rxslp4l rx power slope 4; uns igned fixed-point; msb is at lower physical address. 3a-3b 58-59 2 rxoff4h: rxoff4l rx power offset 4; signed integer; msb is at lower physical address. 3c-3d 60-61 2 rxslp5h: rxslp5l rx power slope 5; uns igned fixed-point; msb is at lower physical address. 3e-3f 62-63 2 rxoff5h: rxoff5l rx power offset 5; signed integer; msb is at lower physical address. 40-41 64-65 2 rxslp6h: rxslp6l rx power slope 6; uns igned fixed-point; msb is at lower physical address. 42-43 66-67 2 rxoff6h: rxoff6l rx power offset 6; signed integer; msb is at lower physical address. 44-45 68-69 2 rxslp7h: rxslp7l rx power slope 7; signed integer; msb is at lower physical address. 46-47 70-71 2 rxoff7h: rxoff7l rx power offset 7; signed fixed-point; msb is at lower physical address. table 12. internal calibration coefficient memory map ? part ii
micrel, inc. MIC3003GFL july 2010 25 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 figure 3. internal calibration rx power linear approximation c/ reading the adc result registers the adc result registers should be read as 16-bit registers under internal calibration while under external calibration they should be read as 8-bit or 16-bit registers at the msb address. for example, tx power should be read under internal calibration as 16 bits at address a2h: 66h?67h and under external calibration as 8 bits at address a2h: 66h. 9- bit temperature results and 12-bit receive power results should always be read as 16-bit quantities. reading the result registers us ing two-byte burst reads on the smbus guarantees that t he two bytes are coherent with each other?that is, they form a matched result pair. if the two bytes were read separ ately, it is possible that the internal result could be updated between the reads, leading to an incorrect adc result. rxpot a programmable, non-volatile digitally controlled potentiometer is provided for adjusting the gain of the receive power measurement signal chain in the analog domain. five bits in the rxpot register are used to set and adjust the position of potentiometer. rxpot functions as a programmable divider or attenuator. it is adjustable in steps from 1:1 (no divider action) down to 1/32 in steps of 1/32. if rxpot is set to zero, then the divider is bypassed comple tely. there will be no scaling of the input signal, and the resistor network will be disconnected from the vrx pin. at all other settings of rxpot, there will be a 32k ? (typical) load seen on vrx. figure 4. rxpot block diagram laser diode bias control the mic3003 can be configured to generate a constant bias current using electrical feedback, or regulate average transmitted optical power using a feedback signal from a monitor photodiode, as shown in figure 5. an operational amplifier is used to control laser bias current via the v bias output. the vbias pin can drive a maximum of 10ma. an external bipolar transistor provides current gain. the polarity of the op amp?s output is programmable with biasref (bit-5 in oemcfg1) in order to accommodate either npn or pnp transistors that drive common anode and common cathode laser, respectively. additionally, the polarity of the feedback signal is programmable for use with either common-emitter or emitter-follower transistor circuits.
micrel, inc. MIC3003GFL july 2010 26 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 furthermore, the reference level for the apc circuit is selectable to accommodate electrical, i.e., current feedback, or optical feedback via a monitor photodiode. finally, any one of seven different internal feedback resistors can be selected. this internal resistor can be used alone or in parallel with an external resistor. this wide range of adjustability (50:1) accommodates a wide range of photodiode current, i.e., wide range of transmitter output power. the apc operating point can be kept near the mid-scale value of the apc dac, insuring maximum snr, maximum effective resolution for digital diagnostics, and the widest possible dac adjustment range for temperature compensation, etc. see figure 6. the apccal bit in oemcal0 is used to turn the apc function on and off. it will be turned on in the mic3003?s default state as shipped from the factory. when the apc is on, the value in the selected apcsetx register is added to the signed compensation value taken from the apc look-up table and loaded into the v bias dac. when the apc is off, the v bias dac may be written directly via the v bias register, bypassing the look-up table entirely. this provides direct control of the laser diode bias during setup and calibration. in either case, the v bias dac setting is reported in the apcdac register. figure 5. apc and modulation control block diagram figure 6. programmable feedback resistor laser modulation control as shown in figure 5, a temperature-compensated dac is provided to set and control the laser modulation current via an external laser driver circuit. the modref bit in oemcfg0 selects whether the v mod dac output swings up from ground or down from v dd . if the laser driver requires a voltage input to set the modulation current, v mod output can drive it directly. if a current input is required, a fixed re sistor can be used between the driver and the v mod output. several different configurations are possible as shown in figure 8. when the apc is on, i.e., the apccal bit in oemcal0 is set to 0, the value corresponding to the current temperature is taken from the modlut look-up table, added to the selected modsetx register, and loaded into the v mod dac. when the apc is off, the compensation value in v mod is loaded directly into the v mod dac, bypassing the look-up table entirely. this provides for direct modulation control for setup and calibration. figure 7. transmitter configurations supported by mic3003
micrel, inc. MIC3003GFL july 2010 27 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 figure 8. v mod configured as voltage output with gain power on and laser start-up when power is applied, t he mic3003 initializes its internal registers and state machine. this process takes t por , about 50ms. following t por , analog-to-digital conversions begin, serial communication is possible, and the por bit and data ready bits may be polled. the first set of analog data will be available t conv after t por . mic3003s are shipped from the factory with the output enable bit, oe, set to zero, off. the power-up default state, therefore, is apc off, v bias , v mod , and shdn outputs disabled. v bias , v mod , and shdn will be floating (high impedance) and the laser diode, if connected, will be off. once the device is incorporated into a transceiver and properly configured, t hen the shutdown states of shdn, v bias , and v mod will be determined by the state of the apc configuration and oe bits. tables 13, 14, and 15 illustrate the shut down states of the various laser control outputs versus the control bits. configuration bits shutdown state oe spol shdn 0 don?t care hi-z 1 0 gnd 1 1 v dd table 13. shutdown state of shdn vs. configuration bits configuration bits v bias shutdown state oe inv biasref v bias 0 don?t care don?t care hi-z 1 don?t care 0 gnd 1 don?t care 1 v dd table 14. shutdown state of v bias vs. configuration bits configuration bits v mod shutdown state oe modref v mod 0 don?t care hi-z 1 0 gnd 1 1 v dd table 15. shutdown state of v mod vs. configuration bits in order to facilitate hot-plugging, the laser diode is not turned on until t init2 after power-on. following t init2 , and assuming txdisable is not asserted, the dacs will be loaded with their initial values. since t conv is much less than t init2 , the first set of analog data, including temperature, is available at t init2 . temperature compensation will be appli ed to the dac values if enabled. apc will begin if oe is asserted. (if the output enable bit, oe, is not set, the v mod , v bias , and shdn outputs will float indefinitely. ) figure 9 shows the power- up timing of the mic3003. if tx disable is asserted at power-up, the v mod and v bias outputs will stay in their shutdown states following mic3003 initialization. a/d conversions will begin, but the laser will remain off.
micrel, inc. MIC3003GFL july 2010 28 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 figure 9. mic3003 power-on timing (oe = 1) fault comparators in addition to detecting and reporting the events specified in sff-8472, the mic3003 also monitors five fault conditions: inadequate supply voltage, thermal diode faults, excessive bias current, excessive transmit power, and apc op-amp saturation. comparators monitor these parameters in order to respond quickly to fault conditions that could indicate link failure or safety issues, see figure 10. when a fault is detected, the laser is shut down and txfault is asserted. each fault source may be independently disabled using the fltmsk register. fltmsk is non-volatile, allowing faults to be masked only during calibration and testing or permanently. figure 10. fault comparator logic
micrel, inc. MIC3003GFL july 2010 29 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 thermal diode faults are detected within the temperature measurement subsystem when an out-of-range signal is detected. a window comparator circuit monitors the voltage on the compensation capacitor to detect apc op- amp saturation (figure 11). op-amp saturation indicates that some fault has occurred in the control loop such as loss of feedback. the saturation detector is blanked for a time, tflttmr, following laser turn-on since the compensation voltage will essentially be zero at turn-on. the flttmr interval is programmable from 0.5ms to 127.5ms (typical) in increm ents of 0.5ms (tflttmr). note that a saturation comparator cannot be relied upon to meet certain eye-safety standards that require 100ms response times. this is because the operation of a saturation detector is limited by the loop bandwidth, i.e., the choice of c comp . even if the comparator itself was very fast, it would be subject to the limited slew-rate of the apc op-amp. only the other fault comparator channels will meet <100ms timing requirements. the mic3003 can also except and respond to fault inputs from external devices. see the ?shdn and txfin? section. a similar comparator circuit monitors received signal strength and asserts rxlos when loss-of-signal is detected (figure 12). rxlos will be asserted if vrx drops below the level programmed in losflt. hysteresis is implemented such that rxlos will be de- asserted when vrx subsequently rises above the level programmed in losfltn. the loss-of-signal comparator may be disabled completely by setting the losdis bit in oemcfg3. once the los comparator is disabled, an external device may drive rxlos. the state of the rxlos pin is reported in the cntrl register regardless of whether it is driven by the internal comparator or by an external device. a programmable digital-to-analog converter provides the comparator reference voltages for monitoring received signal str ength, transmit power, and bias current. since laser bias current varies greatly with temperature, there is a te mperature compensation look- up table for the bias current fault dac value. when a fault condition is detected, the laser will be shutdown immediately and txfault will be asserted. the v mod , v bias , and shdn (if enabled by setting oemcfg5 bit 7 to 1) outputs will be driven to their shutdown state according to th e state of the configuration bits. the shutdown states of v mod , v bias , and shdn versus the configuration bit settings are shown in table 12, table 13, and table 14. shdn and txfin shdn and txfin are optional functions of pin 12. shdn is an output function and is designed to drive a redundant safety switch in the laser current path. txfin is an input function and serves as an input for fault signals from external devices that must be reported to the host via txfault. the shdn function is designed for applications in which the mic3003 is performing all apc and laser management tasks. the txfin function is for situations in which an external device such as a laser diode driver ic is performing laser management tasks, including fault detection. if the txfin bit in oemcfg3 is zero (the default mode), shdn will be activated anytime the laser is off. thus, it will be active if 1) txdisable is asserted, 2) stxdis in the cntrl register, is set, or 3) a fault is detected. shdn is a push-pull logic output. its polarity is programmable via the spol bit in oemcfg1. if txfin bit is set to one, pin 12 serves as an input that accepts fault signals from external devices such as laser diode driver ics. multiple txfault signals cannot simply be wire-or?ed together as they are open-drain and active high. the input polarity is programmable via the txfpol bit in oemcfg3. txfin is logically or?ed with the mic3003?s internal fault sour ces to produce txfault and determine the value of the transmit fault bit in cntrl. see figure 10. figure 11. saturation detector figure 12. rxlos comparator logic
micrel, inc. MIC3003GFL july 2010 30 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 temperature measurement the temperature-to-digital converter is built around a switched current source and an eight-bit/nine-bit analog- to-digital converter. the te mperature is calculated by measuring the forward voltage of a diode junction at two different bias current levels. an internal multiplexer directs the current source?s output to a diode junction. this data is also used as the input to the temperature compensation look-up tables. each time temperature is sampled and an updated value acquired, new corrective values for modulation current and the apc setpoint are read from the corresponding tables, added to the set values, and transferred to the dacs. diode faults the mic3003 is designed to respond in a failsafe manner to hardware faults in the temperature sensing circuitry. if there is a fault with the on-chip sensing diode, the temperature data reported by the a/d converter will be forced to its full-scale value (+127 c). the diode fault flag, dflt, will be set in oemcfg0, txfault will be asserted, and the high temperature alarm and warning flags will be set. the reported temperature will remain at +127 c until the fault condition is cleared. diode faults may be reset by toggling txdisable, as with any other fault. diode faults will not be detected at power up until the first a/d conversion cycle is completed. temperature compensation since the performance characteristics of laser diodes and photodiodes change with operating temperature, the mic3003 provides a facility for temperature compensation of the apc. loop set-point, laser modulation current, bias current fault comparator threshold, and bias current high alarm flag threshold. temperature compensation is performed using a look-up table (lut) that stores values corresponding to each measured temperature over a 150c span. four identical tables reside at serial address a4h and a6h as summarized in table 16. each table entry is a signed twos complement integer that is used as an offset to the parameter being compensated. the default value of all table entries is zero, giving a flat response. the a/d converter reports a new temperature sample each t conv . this occurs at roughly 10 hz when 8-bit temperature resolution is selected. to prevent temperature oscillation due to t hermal or electrical noise, sixteen successive temperature samples are averaged together and used to index the lut.s. temperature compensation results are therefore updated at 16xt conv intervals, or about 1.6 seconds. this can be expressed as shown in equation 8: 16 t ? ? ? + t + t + t = t 15 + n 2 + n 1 + n n compm (8) each time an updated average value is acquired, a new offset value for the apc setpoint is read from the corresponding look-up table (see table 17) and transferred to the apc circuitry. this is illustrated in equation 11. in a same way, new offset values are taken from similar look-up tables (see table 18 and table 19), added to the nominal values and transferred into the modulation and fault comparator dacs. the bias curr ent high alarm threshold is compensated using a fourth look-up table (see table 20). this compensation happens internally and does not affect any host-accessible registers. ) t ( apclut + apcsetx = apcsetm compm max _ table t min _ table compm (max) apclut + apcsetx = apcsetm max _ table > t comp (min) apclut + apcsetx = apcsetm min _ table < t comp (9) if the measured temperature is greater than the maximum table value, the highest value in each table is used. if the measured temperature is less than the minimum, the minimum value is used. hysteresis is employed to further enhance noise immunity and prevent oscillation. each table entry spans two degrees c. the table index will not change unless the new temperature average results in a table index beyond the midpoint of the next entry in either direction. there is therefore 2 to 3c of hysteresis on temperature compensation changes. the table index will never oscillate due to quantization noise as the hysteresis is much larger than 1 2 lsb. serial address byte addresses function 00h?3fh apc look-up table 40h?7fh imod look-up table 80h?bfh iflt look-up table base address +4h c0h?ffh bias high alarm look-up table 58h?63h apc look-up table (cont.) 64h?6fh imod look-up table (cont.) 70h?7bh iflt look-up table (cont.) base address +6h 7ch?87h bias high alarm look-up table (cont.) table 16. temperature compensation look-up tables
micrel, inc. MIC3003GFL july 2010 31 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 serial address register address table offset temperature offset (c) 00h 0 -45 -44 01h 1 -43 ? ? ? ? ? ? ? ? ? 80 base address +4h 3fh 63 81 82 64h 64 83 ? ? ? ? ? ? 102 6e 74 103 base address +6h 6f 75 104 table 17. apc temperature compensation look-up table serial address register address table offset temperature offset (c) 40h 0 -45 -44 41h 1 -43 ? ? ? ? ? ? ? ? ? 80 base address +4h 7fh 63 81 82 70 64 83 ? ? ? ? ? ? 102 7a 74 103 base address +6h 7b 75 104 table 18. i mod temperature compensation look-up table serial address register address table offset temperature offset (c) 80h -45 -44 81h -43 82h ? ? ? ? ? ? ? ? ? beh 80 base address +4h bfh 63 81 82 58 64 83 ? ? ? ? ? ? 102 62 74 103 base address +6h 63 75 104 table 19. i bias comparator temperature compensation look-up table serial address register address table offset temperature offset (c) c0h -45 -44 c1h -43 c2h ? ? ? ? ? ? ? ? ? feh 80 base address +4h ffh 63 81 82 7c 64 83 ? ? ? ? ? ? 87 74 102 base address +6h 103 table 20. bias current high alarm temperature compensation table
micrel, inc. MIC3003GFL july 2010 32 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 the internal state machine calculates a new table index each time a new average temperature value becomes available. this table index is derived from the average temperature value. the table index is then converted into a table address for each of the four look-up tables. these operations can be expressed as: 2 t = index ) n ( avg (10) where tavg(n) is the current average temperature; and table_address=index+base_address where base_address is the physical base address of each table, i.e., 00 h , 20 h , 40 h , 80 h , or 60 h (tables reside in the base address + 4h and base address + 6h pages of memory). at any given time, the current table index can be read in the lutindx register. alarms and warning flags there are 20 different conditions that will cause the mic3003 to set one of the bits in the warnx or alarmx registers. these conditions are listed in table 21. the less critical of these events generate warning flags by setting a bit in warn0 or warn1. the more critical events cause bits to be set in alarm0 or alarm1. an event occurs when any alarm or warning condition becomes true. each event causes its corresponding status bit in alarm0, alar m1, warn0, or warn1 to be set. this action cannot be masked by the host. if oemcfg-4 bits [7-4] are se t to 0 (default value), the status bit will remain set until the host reads that particular status register, a power on-off cycle occurs, or the host toggles txdisable. if txdisable is asserted at any time during normal operation, a/d conversions c ontinue. the a/d results for all parameters will continue to be reported. all events will be reported in the normal way. if they have not already been individually cleared by read operations, when txdisable is de-asserted, a ll status registers will be cleared. control and status i/o the logic for the transceiver control and status i/o is shown schematically in figure 13. note that the internal drivers on rxlos/trsout, rrsout/g po, qgpo, and txfault are all open-drain. these signals may be driven either by the internal logic or external drivers connected to the corresponding mic3003 pins. in any case, the signal level appearing at the pins of the mic3003 will be reported in the control register status bits. note that the control bits for tx_disable and rrsout, trsout, and the status bits for txfault and rxlos do not meet the timing requirements as specified in the sfp msa or the gbic specification, revision 5.5 (sff-8053) for the hardware signals. the speed of the smbus serial interface limits the rate at which these functions can be manipulated and/or reported. th e response time for the control and status bits is given in the ?electrical characteristics? subsection.
micrel, inc. MIC3003GFL july 2010 33 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 event condition mic3003 response temperature high alarm temp > tmax set alarm0[7] temperature low alarm temp < tmin set alarm0[6] voltage high alarm vin > vmax set alarm0[5] voltage low alarm vin < vmin set alarm0[4] tx bias high alarm ibi as > ibmax set alarm0[3] tx bias low alarm ibias < ibmin set alarm0[2] tx power high alarm txop > txmax set alarm0[1] tx power low alarm txop < txmin set alarm0[0] rx power high alarm rxop > rxmax set alarm1[7] rx power low alarm rxop < rxmin set alarm1[6] temperature high warning temp > thigh set warn0[7] temperature low warning temp < tlow set warn0[6] voltage high warning vin > vhigh set warn0[5] voltage low warning vin < vlow set warn0[4] tx bias high warning ibias > ibhigh set warn0[3] tx bias low warning ibias < iblow set warn0[2] tx power high warning txop > txhigh set warn0[1] tx power low warning txop < txlow set warn0[0] rx power high warning rxop > rxhigh set warn1[7] rx power low warning rxop < rxlow set warn1[6] table 21. mic3003 alarm and warning events figure 13. control and status i/o logi
micrel, inc. MIC3003GFL july 2010 34 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 system timing the timing specifications for mic3003 control and status i/o ar e given in the ?electrical ch aracteristics? subsection. figure 14. transmitter on-off timing figure 15. initialization timing with txdisable asserted figure 16. initialization timing with txdisable not asserted
micrel, inc. MIC3003GFL july 2010 35 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 figure 17. loss-of-signal (los) timing figure 18. transmit fault timing
micrel, inc. MIC3003GFL july 2010 36 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 figure 19. successfully clearing a fault condition figure 20. unsuccessful attempt to clear a fault warm resets the mic3003 can be reset to its power-on default state during operation by setting the rst bit in oemcfg0. when this bit is set, txfault and rxlos will be de- asserted, all registers will be restored to their normal power-on default values, and any a/d conversion in progress will be halted and the results discarded. the state of the mic3003 following this operation is indistinguishable from a power-on reset. power-on hour meter the power-on hour meter logs operating hours using an internal real-time clock and st ores the result in nvram. the hour count is incremented at ten-hour intervals in the middle of each interval. the first increment therefore takes place five hours after power-on. time is accumulated whenever the mic3003 is powered. the hour meter?s time base is accurate to +/-10% over all mic3003 operating conditions, and is accurate to +/-5% in the range 0 to 70 degrees c. the counter is capable of storing counts of more than thirty years, but is ultimately limited by the write-cycle endu rance of the non-volatile memory. this implies a range of at least twenty years. actual results will depend upon the operating conditions and write-cycle endurance of the part in question. two registers, pohh and pohl, contain a 15-bit power-on hour measurement and an error flag, pohflt. great care has been taken to make the mic3003?s hour meter immune to data corruption and to insure that valid data is maintained across power cycles. the hour meter employs multiple data copies and error correction codes to maintain data validity. this data is stored in the pohdata registers. if pohflt is set, however, the power-on hour meter data has been corrupted and should be ignored. it is recommended that a two-byte sequential read operation be performed on pohh and pohl to insure coherency between the two registers. these registers are accessible by the oem using a valid oem password. the only operation that should be performed on these registers is to clear the hour meters initial value, if necessary, at the time of product shipment. the hour meter result may be cleared by setting all eight pohdata bytes to 00 h .
micrel, inc. MIC3003GFL july 2010 37 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 test and calibration features numerous features are included in the mic3003 to facilitate development, testing, and diagnostics. these features are available via registers in the oem area. as shown in table 22, these features include: function description control register(s) analog loop-back provides analog visibility of op-amp and dac outputs via the adc oemcfg0 fault comparator disable control disables the fault comparator oemcal0 fault comparator spin-on-channel mode selects a single fault comparator channel oemcal0 fault comparator output read-back allows host to read individual fault comparator outputs oemrd trsout, /int read-back allows host to read the state of these pins oemrd inhibit eeprom write cycles speeds repetitive wr ites to registers backed up by nvram oemcal0 apc calibration mode allows direct writes to moddac and apcdac (temperature compensation not used) oemcal0 continuity checking forcing of rxlos, txfault, /int oemcal0 halt a/d stops a/d conversions; adc in one-shot mode oemcal1 adc idle flag indicates adc status oemcal1 a/d one-shot mode performs a single a/d conv ersion on the selected input channel oemcal1 a/d spin-on-channel mode selects a single input channel oemcal1 channel selection selects adc or fault comparator channel for spin-on-channel modes oemcal1 lut index read-back permits visibility of the lu t index calculated by the state-machine lutindx manufacturer and device id registers facilit ates presence detection and version control mfg_id, dev_id table 22. test and diagnostic features
micrel, inc. MIC3003GFL july 2010 38 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 serial port operation the mic3003 uses standard write byte, read byte, and read word operations for communication with its host. it also supports block write and block read transactions. the write byte operation involves sending the devices address (with the r/w bit low to signal a write operation), followed by the address of t he register to be operated upon and the data byte. the read byte operation is a composite write and read operation: the host first sends the devices address followed by the register address, as in a write operation. a new start bit must then be sent to the mic3003, followed by a repeat of the device address with the r/w bit (lsb) set to the high (read) state. the data to be read from the part may then be clocked out. a read word is similar, but two successive data bytes are clocked out rather than one. these protocols are shown in figures 21 to 24. the mic3003 will respond to up to four sequential device addresses depending upon whether it is in oem or user mode. a match between one of the mic3003?s addresses and the address specified in t he serial bit stream must be made to initiate communication. the mic3003 responds to device addresses a0 h and a2 h in user mode; it also responds to a4 h and a6 h in oem mode (assuming the base address is a0 h ). block writes to increase the speed of block writes, the mic3003 allows up to eight consecutive bytes to be written before the internal memory update begins. the block write sequence begins just like a write byte operation with the host sending the device address, r/w bit low, register address, etc. afte r the first data byte is sent the host will receive an acknowledge. up to seven more bytes can be sent in sequence. the mic3003 will acknowledge each one and increment its internal address register in anticipation of the nex t byte. after the last byte is sent, the host issues a stop. the mic3003?s internal write process then begins. block writes of up to eight bytes can begin and end at any byte address without restriction. block writes that increment over register address ffh will simply ?wrap around? and continue at address 00h within the same device address space. to accelerate calibration and testing, nvram write cycles can be disabled completely by setting the wrinh bit in oemcal0. writes to regist ers that do not have nvram backup, will not incur write-cycle delays when writes are inhibited. write operations on registers that exist only in nvram will still incur write cycle delays. figure 21. write byte protocol figure 22. read byte protocol figure 23. read_word protocol
micrel, inc. MIC3003GFL july 2010 39 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 figure 24. eight-byte block write protocol acknowledge polling the mic3003?s non-volatile memory cannot be accessed during the internal memory update. to allow for maximum speed bulk writes, the mic3003 supports acknowledge polling. the mic3003 will not acknowledge serial bus transactions while internal writes are in progress. the host may therefore monitor for the end of the write process by periodically checking for an acknowledgement. the longest duration for the internal memory update to complete for a block write is approximately 26 ms. write protection and data security oem password a password is required to access the oem areas of the mic3003, specifically the non-volatile memory, look-up tables, and registers at serial addresses a4 h and a6 h . a four-byte field, oempwset, at serial address a6 h is used for setting the oem password. the oem password is set by writing oempwset with the new value. the password comparison is performed following the write to the msb of the oempw, address 7b h (or 7e h if oemcfg5 bit 2 is set to 1) at serial address a2 h . therefore, this byte must be written last. a four-byte burst-write sequence to address 78 h (or 7b h if oemcfg5 bit 2 is set to 1) may be used as this will result in the msbyte being written last. new passwords written to the oempwset registers will not take effect until after a power-on reset occurs or a wa rm reset is performed using the rst bit in oemcfg0. this allows the new password to be verified before it takes effect. the corresponding four-byte field for password entry, oempw, is located at serial address a2 h . this field is therefore always visible to the host system. oempw is compared to the four-byte oempwset field at serial address a6 h . if the two fields match, access is allowed to the oem areas of the mic3003 non-volatile memory at serial addresses a4 h and a6 h . if oempwset is all zeroes, no password security will exist. the value in oempw will be ignored. this helps prevent a deliberately unsecured mic3003 from being inadvertently locked. once a valid password is entered, the mic3003 oem areas will be accessible. the oem areas ma y be re-secured by writing an incorrect password value at oempw, e.g., all zeroes. in all cases, oempw must be written lsb first through msb last. the oem areas will be inaccessible following the final write operation to oempw?s lsb. the oempw field is reset to all zeros at power on. any values written to these locations will be readable by the host regardless of the locked/unlocked status of the device. if oempwset is set to zero (00000000 h ), the mic3003 will remain unlocked regardless of the contents of the oempw field. this is the factory default security setting. note that a valid oem password allows access to the oem and user areas of the chip, i.e., the entire memory map. oem mode and user mode when the oem password is unlocked (either by matching the set password or if the password is all zeros), the mic3003 is in oem mode. if the part is locked, the part is in user mode.
micrel, inc. MIC3003GFL july 2010 40 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 detailed register descriptions note: serial bus addresses shown assu me that the base device address is ao h . alarm threshold registers temperature high alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 c) serial address a2 h byte addresses ms byte (tmaxh): 00 = 00 h ls byte (tmaxl): 01 = 01 h each ls bit of tmaxh represents one degree celsius. tmaxl is not used, since all limit co mparisons for temperature use eight-bit values. the eight bits of the high alarm threshold value (tmaxh) are compared to the temperature result (temph). alarm0 bit 7 is set if result > threshold. temperature low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 c) serial address a2 h byte addresses ms byte (tminh): 02 = 02 h ls byte (tminl): 03 = 03 h each ls bit of tminh represents one degree celsius. tminl is not used, since all limit compar isons for temperature use eight- bit values.. the eight ms bits of the low alarm threshold value (tminh) are compared to the temperature result (temph). alarm0 bit 6 is set if result < threshold. voltage high alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 v) serial address a2 h byte addresses ms byte (vmaxh): 08 = 08 h ls byte (vmaxl): 09 = 09 h each ls bit of vmaxh represents 25.6 mv and each ls bit of vmaxl represents 0.1 mv. the sixteen-bit threshold value (vmaxh:vmaxl) is compared to the sixteen bits value of the voltage result (vinh:vinl) . alarm0 bit 5 is set if result > threshold.
micrel, inc. MIC3003GFL july 2010 41 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 voltage low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 v) serial address a2 h byte addresses ms byte (vminh): 10 = 0a h ls byte (vminl): 11 = 0b h each ls bit of vminh represents 25.6 mv and each ls bit of vminl represents 0.1 mv. t he sixteen-bit threshold value (vminh:vminl) is compared to the sixteen-bi t value of the voltage result (vinh:vinl). al arm0 bit 4 is set if result < threshold . bias current high alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 ma) serial address a2 h byte addresses ms byte (imaxh): 16 = 10 h ls byte (imaxl): 17 = 11 h each ls bit of imaxh represents 512 a and each ls bit of imaxl represents 2 a. the sixteen-bit threshold value (imaxh:imaxl) is compared to the sixteen-bi t value of the bias current result (ildh :ildl). alarm0 bit 3 is set if result > threshold. bias current low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 ma) serial address a2 h byte addresses ms byte (iminh): 18 = 12 h ls byte (iminl): 19 = 13 h each ls bit of iminh represents 512 a and each ls bit of iminl represents 2 a. the sixteen-bit threshold value (iminh:iminl) is compared to the sixt een-bit value of the bias current result (ildh:ildl). alarm0 bit 2 is set if result < threshold. tx optical power high alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 mw) serial address a2 h byte addresses ms byte (txmaxh): 24 = 18 h ls byte (txmaxl): 25 = 19 h each ls bit of txmaxh represents 25.6 w, and each ls bit of txmaxl represents 0.1 w. the sixteen-bit threshold value (txmaxh:txmaxl) is compared to the sixteen- bit value of the tx power result (txoph:t xopl). alarm0 bit 1 is set if result > threshold.
micrel, inc. MIC3003GFL july 2010 42 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 tx optical power low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 mw) serial address a2 h byte addresses ms byte (txminh): 26 = 1a h ls byte (txminl): 27 = 1b h each ls bit of txminh represents 25.6 w, and each ls bit of txminl represents 0.1 w. the sixteen-bit threshold value (txminh:txminl) is compared to the sixteen-bit value of t he tx power reading (txoph:txopl). alarm0 bit 0 is set if result < threshold. rx optical power high alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 mw) serial address a2 h bytes addresses ms byte (rxmaxh): 32 = 20 h ls byte (rxmaxl): 33 = 21 h each ls bit of rxmaxh represents 25.6 w, and each ls bit of rxmaxl represents 0.1 w. the sixteen-bit threshold value (rxmaxh:rxmaxl) is compared to the sixteen-bit value of the rx power result (rxoph:rxopl ). alarm1 bit 7 is set if result > threshold. rx optical power low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0mw) serial address a2 h byte address ms byte (rxminh): 34 = 22 h ls byte (rxminl): 35 = 23 h each lsb of rxminh represents 25.6 w, and each ls bit of rxminl represents 0.1 w. the sixteen-bit threshold value (rxminh:rxminl) is compared to the sixteen-bit value of t he rx power result (rxoph:rxopl ). alarm1 bit 6 is set if result < threshold.
micrel, inc. MIC3003GFL july 2010 43 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 warning threshold registers temperature high warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 c) serial address a2 h bytes addresses ms byte (thighh): 04 = 04 h ls byte (thighl): 05 = 05 h each ls bit of thighh represents one degree celsius. thighl is not used, since al l limit comparisons for temperature use eight-bit values. the eight bits of the high warning threshold value (thighh) ar e compared to the temperature result (temph). warn0 bit 7 is set if result > threshold. temperature low warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 c) serial address a2 h bytes addresses ms byte (tlowh): 06 = 06 h ls byte (tlowl): 07 = 07 h each ls bit of tlowh represents one degree celsius. tlowl is not used, since all limit co mparisons for temperature use eight-bit values. the eight bits of the high warning threshold value (tlowh) ar e compared to the temperature result (temph). warn0 bit 6 is set if result < threshold. voltage high warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 v) serial address a2 h bytes addresses ms byte (vhighh): 12 = 0c h ls byte (vhighl): 13 = 0d h each ls bit of vhighh represents 25.6 mv and each ls bit of vhighl represents 0.1 mv. the sixteen-bit threshold value (vhighh:vhighl) is compared to the si xteen bits value of the voltage result (vinh:vinl). warn0 bit 5 is set if result > threshold.
micrel, inc. MIC3003GFL july 2010 44 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 voltage low warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 v) serial address a2 h byte addresses ms byte (vlowh): 14 = 0e h ls byte (vlowl): 15 = 0f h each ls bit of vlowh represents 25.6 mv and each ls bit of vlowl represents 0.1 mv. the sixteen-bit threshold value (vlowh:vlowl) is compared to the sixteen-bit value of the voltage result (vinh:vinl). warn0 bit 4 is set if result < threshold. bias current high warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 ma) serial address a2 h bytes addresses ms byte (ihighh): 20 = 14 h ls byte (ihighl): 21 = 15 h each ls bit of ihighh represents 512 a and each ls bit of ihighl represents 2 a. the sixteen-bit threshold value (ihighh:ihighl) is compared to the sixteen-bit value of the bias current result (ild h:ildl). warn0 bit 3 is set if result > threshold. bias current low warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 ma) serial address a2 h bytes addresses ms byte (ilowh): 22 = 16 h ls byte (ilowl): 23 = 17 h each ls bit of ilowh represents 512 a and each ls bit of ilowl represents 2 a. the sixteen-bit threshold value (ilowh:ilowl) is compared to the sixteen-bit value of t he bias current result (ildh:ildl). warn0 bit 2 is set if result < threshold. tx optical power high warning d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 mw) serial address a2 h bytes addresses ms byte (txhighh): 28 = 1c h ls byte (txhighl): 29 = 1d h each ls bit of txhighh represents 25.6 w, and each ls bit of txhighl represents 0.1 w. the sixteen-bit threshold value (txhighh:txhighl) is compared to the sixteen-bit value of the tx power result (txoph:txopl).warn0 bit 1 is set if result > threshold.
micrel, inc. MIC3003GFL july 2010 45 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 tx optical power low warning d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 mw) serial address a2 h byte addresses ms byte (txlowh): 30 = 1e h ls byte (txlowl): 31 = 1f h each ls bit of txlowh represents 25.6 w, and each ls bit of txlowl represents 0.1 w. the sixteen-bit threshold value (txlowh:txlowl) is compared to the sixte en-bit value of the tx power reading (txoph:txopl). alarm0 bit 0 is set if result < threshold. rx optical power high warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 mw) serial address a2 h byte addresses ms byte (rxhighh): 36 = 24 h ls byte (rxhighl): 37 = 25 h each ls bit of rxhighh represents 25.6 w, and each ls bit of rxhighl represents 0.1 w. the sixteen-bit threshold value (rxhighh:rxhighl) is compared to the sixteen-bit value of t he rx power result (rxoph:rxopl). warn1 bit 7 is set if result > threshold. rx optical power low warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for both bytes 0000 0000 b = 00 h (0 mw) serial address a2 h byte addresses ms byte (rxlowh): 38 = 26 h ls byte (rxlowl): 39 = 27 h each lsb of rxlowh represents 25.6 w, and each ls bit of rxlowl represents 0.1 w. the sixteen-bit threshold value (rxlowh:rxlowl) is compared to the sixteen-bit value of t he rx power result (rxoph:rxopl). warn1 bit 6 is set if result < threshold. checksum (chksum) checksum of bytes 0 - 94 at serial address a2h d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a2 h byte address 95 = 5f h this register is provided for compliance with sff-8472. it is implemented as general-purpose non-volatile memory. read/write access is possible whenever a valid oem password has been entered. chksum is read-only in user mode.
micrel, inc. MIC3003GFL july 2010 46 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 adc result registers temperature result d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only serial address a2 h byte addresses ms byte (temph): 96 = 60 h ls byte (templ): 97 = 61 h each ls bit of temph represents one degree celsius. the te mph register is to be used in conjunction with the most significant bit of templ to yield an eight-bit or ni ne-bit signed (two?s complement) temperature value. if oemcfg6 bit 1 is set to zero, temperature is read to 1 c resolution in temph only, and templ is zero. if oemcfg6 bit 1 is set to one, then temperature is read to 0. 5 c resolution as a nine-bit value consisting of temph and the ms bit of templ. the lower seven bits of templ are zero. temph will contain measured temperature dat a after the completion of one conversion. voltage d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value 0000 0000 b = 00 h (0v) (2) serial address a2 h byte addresses ms byte (vinh): 98 = 62 h ls byte (vinl): 99 = 63 h each lsb of vinh represents 25.6 mv, and each ls bit of vinl represents 0.1 mv. vinh is used in conjunction with vinl to yield an unsigned sixteen-bit value. in external calibration mode, the host should process the resu lts using the appropriate slope and offset coefficients. vinh contains the eight-bit a dc result and vinl is zero. in internal calibration mode, the mic3003?s alu applies t he coefficients stored in (vslph:vslpl) and (voffh:voffl). the vin registers will contain valid data after one adc conversion cycle. notes: 1. temph will contain measured temperature dat a after the completion of one conversion. 2. vinh will contain measured data after one a/d conversion cycle. laser diode bias current d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value 0000 0000 b = 00 h (0ma) (3) serial address a2 h byte addresses ms byte (ildh):100 = 64 h ls byte (ildl):101 = 65 h each lsb of ildh represents 512 a, and each ls bit of ildl represents 2 a. ildh is used in conjunction with ildl to yield an unsigned sixteen-bit value. in external calibration mode, the host should process the resu lts using the appropriate slope and offset coefficients. ildh contains the eight-bit adc result and ildl is zero. in internal calibration mode, the mic3003?s alu applies the coefficients stored in (islph:islpl) and (ioffh:ioffl). the ild registers will contain valid data after one adc conversion cycle.
micrel, inc. MIC3003GFL july 2010 47 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 transmitted optical power d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value 0000 0000 b = 00 h (0mw) (4) serial address a2 h byte address ms byte (txoph): 102 = 66 h ls byte (txopl): 103 = 67 h each lsb of txoph represents 25.6 w, and each ls bit of txopl represents 0.1 w. txoph is used in conjunction with txopl to yield an unsigned sixteen-bit value. in external calibration mode, the host should process the resu lts using the appropriate slope and offset coefficients. txoph contains the eight-bit adc result and txopl is zero. in internal calibration mode, the mic3003?s alu applies t he coefficients stored in (txslph:txslpl) and (txoffh:txoffl). the txop registers will contain vali d data after one adc conversion cycle. notes: 3. ildh will contain measured data after one a/d conversion cycle. 4. txoph will contain measured data after one a/d conversion cycle. received optical power d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value 0000 0000 b = 00 h (0mw) (6) serial address a2 h byte address ms byte (rxoph): 104 = 68 h ls byte (rxopl): 105 = 69 h each lsb of rxoph represents 25.6 w, and each ls bit of rxopl represents 0.1 w.rxoph is used in conjunction with rxopl to yield an unsigned sixteen-bit value. in external calibration mode, the host should process the resu lts using the appropriate slope and offset coefficients. rxoph contains the twelve-bit adc result and th e lower four bits of rxopl are zero. in internal calibration mode, the mic3003?s alu applies the coefficients stored in (rxslp[0-7]h:rxslp[0-7]l) and (rxoff[0-7]h:rxoffl[0-7]). the rxop registers will contain vali d data after one adc conversion cycle. control and status (cntrl) d[7] txdis read-only d[6] stxdis read/write d[5] rs1s read-only d[4] rs0s read-only d[3] srs0 read/write d[2] txflt read-only d[1] los read-only d[0] por read-only default value 0000 0000 b = 00 h serial address a2 h byte address 110 = 6e h
micrel, inc. MIC3003GFL july 2010 48 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 bit(s) function operation d[7] txdis reflects the state of the txdisable pin 1 = disabled, 0 = enabled d[6] stxdis soft transmit disable stxdis is ored with txdis to control the laser which will be turned off if one of these two signals is set to 1 1 = disabled 0 = enabled d[5] rs1s reflects the state of rs1 (p in 10) 1 = rs1 is high (>4.25 gbps); 0 = rs1 is low ( 4.25 gbps) d[4] rs0s reflects the state of rs0 (p in 4) 1 = rs0 is high (>4.25 gbps) 0 = rs0 is low ( 4.25 gbps) d[3] srs0 soft rate select (sets the state of the rs0 pin) 1 = set rs0 high 0 = set rs0 low d[2] txflt reflects the st ate of the txfault pin 1 = txfault is high (fault) 0 = txfault low (no fault) d[1] los loss of signal. reflects the state of the rxlos pin 1 = rxlos is high (loss of signal) 0 = rxlos is low (no loss of signal) d[0] por mic3003 power-on status 0 = por complete, all analog data results have been converted at least once 1 = por and first adc sample cycle in progress application select control mode (ascm) d[7-6] control bits read/write d[5-0] table select read/write default value 0000 0000 b = 00 h serial address a2 h byte address 111 = 6f h bit(s) function operation d[7-6] application select control bits d[5-0] table select
micrel, inc. MIC3003GFL july 2010 49 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 bit 7 bit 6 0 0 rate select/extended rate select emulation mode: ? rs0 (pin 4) controls rrsout( pin 23) ? rs1 (pin 10) does not control trsout (pin24) ? byte 110 bit 3 controls rrsout (pin 23) ? byte 118 bit 3 controls trsout (pin 24) 0 1 hardware application select mode: ? rs0 (pin 4) controls rrsout( pin 23) ? rs1 (pin 10) controls trsout (pin 24) ? byte 110 bit 3 does not control rrsout (pin 23) ? byte 118 bit 3 does not control trsout (pin 24) 1 x software mode: ? rs0 (pin4) does not control rrsout( pin 23) ? rs1 (pin10) does not control trsout (pin 24) ? byte 110 bit 3 does not control rrsout (pin 23) ? byte 118 bit 3 does not control trsout (pin 24)
micrel, inc. MIC3003GFL july 2010 50 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 alarm flags alarm status register 0 (alarm0) d[7] a7 read-only d[6] a6 read-only d[5] a5 read-only d[4] a4 read-only d[3] a3 read-only d[2] a2 read-only d[1] a1 read-only d[0] a0 read-only default value 0000 0000 b = 00 h (no events pending) serial address a2 h byte address 112 = 70 h the power-up default value is 00 h . following the first complete a/d conversion cy cle, however, any of the bits may be set depending upon the results. bit(s) function operation d[7] a7 high temperature alarm, temp > tmax 1 = condition exists, 0 = normal/ok d[6] a6 low temperature alarm, temp < tmin 1 = condition exists, 0 = normal/ok d[5] a5 high voltage alarm, vin > vmax 1 = condition exists, 0 = normal/ok d[4] a4 low voltage alarm, vin < vmin 1 = condition exists, 0 = normal/ok d[3] a3 high laser diode bias alarm, ibias > imax 1 = condition exists, 0 = normal/ok d[2] a2 low laser diode bias alarm, ibias < imin 1 = condition exists, 0 = normal/ok d[1] a1 high transmit optical power alarm, txop > txmax 1 = condition exists, 0 = normal/ok d[0] a0 low transmit optical power alarm, txop < txmin 1 = condition exists, 0 = normal/ok alarm status register 1 (alarm1) d[7] a15 read-only d[6] a14 read-only d[5] reserved d[4] reserved d[3] reserved d[2] reserved d[1] reserved d[0] reserved default value 0000 0000 b = 00 h (no events pending) serial address a2 h byte address 113 = 71 h the power-up default value is 00 h . following the first complete a/d conversion cycl e, however, either of the bits may be set depending upon the results. bit(s) function operation d[7] a15 high received power (overload) alarm, rx op > rxmax 1 = condition exists, 0 = normal/ok d[6] a14 low received power (los) alarm, rxop < rxmin 1 = condition exists, 0 = normal/ok d[5:0] reserved reserved, returns zero on reads
micrel, inc. MIC3003GFL july 2010 51 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 warning flags warning status register 0 (warn0) d[7] w7 read-only d[6] w6 read-only d[5] w5 read-only d[4] w4 read-only d[3] w3 read-only d[2] w2 read-only d[1] w1 read-only d[0] w0 read-only default value 0000 0000 b = 00 h (no events pending) serial address a2 h byte address 116 = 74 h the power-up default value is 00 h . following the first complete a/d conversion cy cle, however, any of the bits may be set depending upon the results. bit(s) function operation d[7] w7 high temperature warning, temp > thigh 1 = condition exists, 0 = normal/ok d[6] w6 low temperature warning, temp < tlow 1 = condition exists, 0 = normal/ok d[5] w5 high voltage warning, vin > vhigh 1 = condition exists, 0 = normal/ok d[4] w4 low voltage warning, vin < vlow 1 = condition exists, 0 = normal/ok d[3] w3 high laser diode bias warning, ibias > ihigh 1 = condition exists, 0 = normal/ok d[2] w2 low laser diode bias warning, ibias < ilow 1 = condition exists, 0 = normal/ok d[1] w1 high transmit optical power warning, txop > txhigh 1 = condition exists, 0 = normal/ok d[0] w0 low transmit optical power warning, txop < txlow 1 = condition exists, 0 = normal/ok warning status register 1 (warn1) d[7] w15 read-only d[6] w14 read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value 0000 0000 b = 00 h (no events pending) serial address a2 h byte address 117 = 75 h the power-up default value is 00 h . following the first complete a/d conversion cycl e, however, either of the bits may be set depending upon the results. bit(s) function operation d[7] w15 received power high warning, rxop > rxhigh 1 = condition exists, 0 = normal/ok d[6] w14 received power low warning, rxop < rxmin 1 = condition exists, 0 = normal/ok d[5:0] reserved reserved, returns zero on reads
micrel, inc. MIC3003GFL july 2010 52 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 extended control and status (ecntrl) d[7] reserved d[6] reserved d[5] reserved d[4] reserved d[3] srs1 read/write d[2] reserved d[1] plos read/write d[0] pls read/write default value 0000 0000 b = 00 h serial address a2 h byte address 118 = 76 h bit(s) function operation d[7-4] reserved reserved?always read as zeros d[3] srs1 soft ra te select (rs1) assert the trsout pin in rate select/extended rate select emulation mode d[2] reserved reserved?always reads as zero d[1] plos power level operation state d[0] pls power level select these two bits are read/write but change no functionality of the mic3003 oem password entry (oempw) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for all four bytes 0000 0000 b = 00 h (reset to zero at power-on) serial address a2 h byte addresses if oemcfg5-2 = 0: 120 ? 123 = 78 h ? 7b h if oemcfg5-2 = 1: 123 ? 126 = 7b h ? 7e h this four-byte field is for entry of the password required to access the oem area of the mic30 03?s memory and registers. a valid oem password will also permit access to the user areas of memory. this field is compared to the four-byte oempwset field at serial address a6h, bytes 12 - 15 (0c h ? 0f h ). if the two fields match, access is allowed to the oem areas of the mic3003 non-volatile memory at serial addresses a4 h and a6 h . the oem password is set by writing the new value into oempwset. the password comparison is performed following the write to the highest address byte of oempw, address 7b h if oemcfg5 bit 2 is low, or 7e h if oemcfg5 bit 2 is high. this byte must be written last. a four-byte burst-write sequence to oempw may be used as th is will result in the highest address byte being written last. oempw is reset to zero at power on. any values written to oempw will be readable by the host regardless of the locked/unlocked status of the device. if oempwset is set to zero (00000000 h ), the mic3003 will remain unlocked regardless of the contents of the oempw field. this is the factory default security setting. byte weight 3 oem password entry, most significant byte (address = 7bh resp. 7eh) 2 oem password entry, 2nd most significant byte (address = 7ah resp. 7dh) 1 oem password entry, 2nd least significant byte (address = 79h resp. 7ch) 0 oem password entry, least significant byte (address = 78h resp. 7bh)
micrel, inc. MIC3003GFL july 2010 53 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 power-on hours (pohh and pohl) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value of both bytes when the mic3003 is shipped from the factory 0000 0000 b = 00 h serial address a6 h bytes addresses ms byte (pohh): 251 = fb h ls byte (pohl): 252 = fc h the lower seven bits of pohh contain the most significant bi ts of the 15-bit power-on hours measurement. the value in pohh should be combined with the eight-bit power-on hour s low byte, pohl, to yiel d the complete result. the most significant bit of pohh, pohflt, is an error flag. if pohflt is set, the power-on hour meter data has been corrupted and should be ignored. it is recommended that a two-byte sequential (block) smbu s read operation be performed on pohh and pohl to insure coherency between the two registers. this register is non-volatile and will be maintained through power and reset cycles, including unanticipated power failures. pohh bit(s) function operation d[7] power-on hours fault flag, pohflt 1 = fault: the power-on hours value is corrupted and cannot be relied upon 0 = no fault: the power-on hours value is correct d[6:0] power-on hours, most significant seven bits data ready flags (datardy) d[7] trdy read/write d[6] vrdy read/write d[5] irdy read/write d[4] txrdy read/write d[3] rxdy read/write d[2] reserved d[1] reserved d[0] reserved default value 0000 0000 b = 00 h serial address a6 h byte address 253 = fd h when the a/d conversion for a given paramet er is completed and the results availa ble to the host, the appropriate data ready flag will be set. the flag will be cleared when the host reads the corresponding result register. bit(s) function operation d[7] trdy temperature data ready flag 0 = result register contai ns old data; 1 = new data ready d[6] vrdy voltage data ready fl ag 0 = result register contains old data; 1 = new data ready d[5] irdy bias current data ready flag 0 = result register contains old data; 1 = new data ready d[4] txrdy transmit power data ready flag 0 = result register contains old data; 1 = new data ready d[3] rxrdy receive power data ready flag 0 = result register contains old data; 1 = new data ready d[2:0] reserved reserved
micrel, inc. MIC3003GFL july 2010 54 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 user control register (usrctl) d[7] reserved read/write d[6] porm read/write d[5] pors read/write d[4] ie read/write d[3] apcsel read/write d[2] apcsel read/write d[1] apcsel read/write d[0] modsel read/write default value 0010 0000 b = 20 h serial address a2 h byte address 254 = fe h this register provides for control of the nominal apc setp oint and management of interrupts by the end-user. apcsel[1:0] select which of the apc setpoint registers, apcset0, apc set1, or apcset2 are used as the nominal automatic power control setpoint. similarly, modsel[1:0] select which of modset0, modset1, or mods et2 are used to select the modulation level of the laser. ie must be set for any host interrupts to occur via the /int pi n. if ie is set while /int is asserted, /int will be de-asserted immediately. pors is always set high by any power-on reset event. if porm is high, the power-on event will also generate a host interrupt. pors will be cleared to zero and the interrupt output de-asserted when usrctl is read by the host. if porm is set following the setting of pors, pors will remain set, and /int will be asserted immediately. /int will not be de- asserted until usrctl is read by the host. porm, ie, apcsel, and modsel are non-volatile and will be maintained through power and reset cycles. bit(s) function operation d[7] reserved always write as zero; reads undefined. d[6] porm power-on interrupt ma sk 1 = por interrupts mask enabled 0 = por interrupts mask disabled d[5] pors power-on interrupt flag 1 = por interrupt occurred 0 = no por interrupt d[4] ie global interrupt enable 1 = host interrupts are enabled 0 = host interrupts are disabled d[3:2] apcsel selects apc se tpoint register 00 = apcset0 01 = apcset1 10 = apcset2 11 = reserved d[1:0] modsel selects modulation setpoint register 00 = modset0 01 = modset1 10 = modset2 11 = reserved resetout d[7] reserved read-only d[6] reserved read-only d[5] reserved read-only d[4] reserved read-only d[3] reserved read-only d[2] resetout read/write d[1] resetout read/write d[0] resetout read/write default value 0000 0000 b = 00 h serial address a2 h byte address 255 = ff h
micrel, inc. MIC3003GFL july 2010 55 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 bit(s) function operation d[7-3] reserved read-only; these bits always return 00000. d[2:0] resetout controls the reset output at pin 2 (qgpo) when reset mode is selected (oemcfg3-7 set to 1) by default, these three bits are 000, and the qgpo output is undriven. if reset mode is selected in oemcfg3: when the three bits are written to 111, qgpo?s open-drain output will be driven low for 125 s (typical), after which qgpo reenters the undriven state. the resetout field is cleared from 111 to 000 22.5 ms (typical) after the de-assertion edge of qgpo. other values of this delay may be selected in the trstclr[2:0] field in oemcfg2. if reset mode in oemcfg3 is not selected, these three bits have no function. oem configuration register 0 (oemcfg0) d[7] rst write only d[6] qgpos read/write d[5] dflt read-only d[4] oe reserved d[3] modref reserved d[2] vaux[2] read/write d[1] vaux[1] read/write d[0] vaux[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 00 = 00 h a write to oemcfg0 will result in any a/d conversion in progre ss being aborted and the result discarded. the a/d will begin a new conversion sequence once the write operation is complete. all bits in oemcfg0 are non-volatile except dflt and rst. a valid oem password is required for access to this register. bit(s) function operation d[7] rst 0 = no action; 1 = reset issuing a software reset by setting rst high is equivalent to a full power cycle of the mic3003. d[6] qgpos determines the state of qgpo in gpo mode if oemcfg3 bit 7 (qgpom) is low, this bit determines whether the qgpo output is high (undriven) or low (driven- open-drain). if qgpom is high (reset mode), this bit has no function d[5] dflt diode fault flag. 1 = diode fault; 0 = ok. d[4] oe output enable for shdn, v mod , and v bias . 1 = enabled; 0 = hi-z d[3] modref selects whether v mod is referenced to ground or v dd . 1 = v dd ; 0 = gnd d[2:0] vaux[2:0] selects the voltage reported in vinh:vinl. 000 = v in 001 = v dda 010 = v bias 011 = v mod 100 = apcdac 101 = moddac 110 = fltdac
micrel, inc. MIC3003GFL july 2010 56 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 oem configuration register 1 (oemcfg1) d[7] inv read/write d[6] gain read/write d[5] biasref read/write d[4] rfb[2] read/write d[3] rfb[1] read/write d[2] rfb[0] read/write d[1] srce read/write d[0] spol read/write default value 0000 0010 b = 02 h serial address a6 h byte address 1 = 01 h a write to oemcfg1 will result in any a/d conversion in progre ss being aborted and the result discarded. the a/d will begin a new conversion sequence once the write operation is complete. all bits in oemcfg1 are non-volatile and will be maintained through power and reset cycles. a valid oem password is required for access to this register. bit(s) function operation d[7] inv inverts the apc op-amp inputs. when low, the bias dac output is connected to the ?+?input and fb is connected to the ??? input of the op amp. set low to use the apc feedback loop. 0 = emitter follower (no inversion); 1 = common emitter (inverted); read/write; non-volatile. d[6] gain sets the feedback voltage range by changing the apcdac output swing; 0-v ref for optical feedback, 0-v ref /4 for electrical feedback. 1 = v ref /4 full scale; 0 = v ref full scale d[5] biasref selects whether fb and vmpd are referenced to ground or v dd and selects feedback re sistor termination voltage (v dda or gnda). 1 = v dd ; 0 = gnda if this bit is set to 0, bit 1 should be set to 1 if this bit is set to 1, bit 1 should be set to 0 d[4:2] rfb[2:0] selects internal feedback resistance. resistors will be terminated to v dda or gnda according to biasref. 000 = 001 = 800 ? 010 = 1.6k ? 011 = 3.2k ? 100 = 6.4k ? 101 = 12.8k ? 110 = 25.6k ? 111 = 51.2k ? d[1] srce v bias source or sink drive. 1 = source (npn): bit 5 should be set to 0. 0 = sink (pnp): bit 5 should be set to 1. d[0] spol polarity of the shutdown output, shdn, when active. 1 = shdn is active-high 0 = shdn is active-low
micrel, inc. MIC3003GFL july 2010 57 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 oem configuration register 2 (oemcfg2) d[7] smbadr[3] read/write d[6] smbadr[2] read/write d[5] smbadr[1] read/write d[4] smbadr[0] read/write d[3] read/write d[2] trstclr[2] read/write d[1] trstclr[1] read/write d[0] trstclr[0] read/write default value 1010 0010 b = xx h (device address = 1010 xxxx b ) this value is the basis for using a0 h , a2 h , a4 h , and a6 h as the names of the different device address spaces of the mic3003. serial address a6 h byte address 2 = 02 h caution: changes to smbadr take effect immediately. any accesses following a write to smbadr must be to the newly programmed serial bus address. a valid oem password is required for acce ss to this register. this register is non-volatile and will be maintained through powe r and reset cycles. bit(s) function operation d[7:4] smbadr[3:0] most significant four bits of the serial bus device address writes take effect immediately. d[3:0] trstclr[2:0] set the delay between qgpo and the clearing of resetout these three bits set the delay between the de-assertion edge of the qgpo output in reset mode and the subsequent clearing of the three resetout bits in the resetout register: 000: zero delay 001: 17.5 ms typical 010: 22.5 ms typical (default) 011: 27.0 ms typical 100: 45 ms typical minimum and maximum values may be found by adding tolerances of -10% and +10% to the above values. if reset mode is not selected, these bits have no function.
micrel, inc. MIC3003GFL july 2010 58 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 apc setpoint 0, 1, and 2 (apcset0, apcset1, apcset2) automatic power control setpoint d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for all three bytes 0000 0000 b = 00 h serial address a6 h byte addresses apcset0: 3 = 03 h apcset1: 4 = 04 h apcset2: 5 = 05 h when the apc is on, the eight-bit signed integer compensation va lue corresponding to the current temperature is taken from the biaslut look-up table, added to the selected apcset (0, 1, or 2) register and loaded into the v bias dac. if dac calibration mode is selected in oemcal0, a write to any one of the three apcset n registers will cause the v bias dac to be updated immediately. dac calibration mode disables t he output of the biaslut look up table, so the unmodified apcsetn register value propagat es directly to the dac. the eight-bit value presented to the v bias dac is always available for read back in the apcdac register. a valid oem password is required for access to these register s. these registers are non-volatile and will be maintained through power and reset cycles. modulation setpoint 0, 1, and 2 (modset0, modset1, and modset2) nominal v mod setpoint d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for all three bytes 0000 0000 b = 00 h serial address a6 h byte address modset0: 6 = 06 h modset1: 30 = 1e h modset2: 31 = 1f h when the apc is on, the eight-bit signed integer compensation va lue corresponding to the current temperature is taken from the modlut look-up table, added to the selected modset (0, 1, or 2) register and loaded into the v mod dac. if dac calibration mode is selected in oemcal0, a write to any one of the three modsetn registers will cause the v mod dac to be updated immediately. dac calibration mode disables t he output of the modlut look up table, so the unmodified modsetn register value propagat es directly to the dac. the eight-bit value presented to the v mod dac is always available for read back in the moddac register. a valid oem password is required for access to these register s. these registers are non-volatile and will be maintained through power and reset cycles.
micrel, inc. MIC3003GFL july 2010 59 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 i bias fault threshold (ibflt) bias current fault threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 7 = 07 h when the fault comparator is running, the eight-bit signed integer compensat ion value corresponding to the current temperature is taken from the iftlut look -up table, added to ibflt, and used for comp arison with the laser bias current value for fault generation. faults are generated if the bias current value exceeds the compensated (lut offset) ibflt register contents. if dac calibration mode is selected in oemcal0, the output of t he iftlut lookup table is disabled, so the unmodified ibflt register value propagates directly to the fault comparator dac. a valid oem password is required for access to these register s. these registers are non-volatile and will be maintained through power and reset cycles. transmit power fault threshold (txflt) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 8 = 08 h when the fault comparator is running the tx flt register value is used for comparison with the transmit power value for fault generation. faults are generated if the transmit power exceeds the txflt register contents. a valid oem password is required for acce ss to this register. this register is non-volatile and will be maintained through powe r and reset cycles. loss-of-signal threshold (losflt) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 9 = 09 h when the fault comparator is running, a f ault is generated if the received power is lower than the losflt value set in this register. a valid oem password is required for access to this register. this register is non-volatile and will be maintained through pow er and reset cycles.
micrel, inc. MIC3003GFL july 2010 60 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 fault suppression timer (flttmr) fault suppression interval in increments of 0.5 ms d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 10 = 0a h saturation faults are suppressed for a time, t flttmr , following laser turn-on. this avoids nuisance tripping while the apc loop starts up. the length of this interval is (flttmr x 0.5 ms), typical. a value of zero will result in no fault suppression. a valid oem password is required for acce ss to this register. this register is non-volatile and will be maintained through powe r and reset cycles. fault mask (fltmsk) d[7] oemim read/write d[6] pohe read/write d[5] reserved d[4] reserved d[3] satmsk read/write d[2] txmsk read/write d[1] iamsk read/write d[0] dfmsk read/write default value 0000 0000 b = 00 h serial address a6 h byte address 11 = 0b h a valid oem password is required for acce ss to this register. this register is non-volatile and will be maintained through powe r and reset cycles. bit function operation d[7] oemim oem interrupt mask 1 = interrupts are masked 0 = interrupts are enabled this bit is similar to the ie (global interrupt enable) bit in the user control register. the /int output can only be asserted if ie is high and oemim is low. d[6] pohe oem power-on hour meter enable 1 = power-on hour meter enabled 0 = power-on hour meter disabled d[5:4] d[5:4] reserv ed always write as zero; reads undefined d[3] satmsk apc saturation fault mask 1 = masked; 0 = enabled d[2] txmsk high tx optical power fault mask 1 = masked; 0 = enabled d[1] iamsk high bias current high fault mask 1 = masked; 0 = enabled d[0] dfmsk diode fault mask 1 = masked; 0 = enabled
micrel, inc. MIC3003GFL july 2010 61 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 oem password setting (oempwset) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value for all bytes 0000 0000 b = 00 h serial address a6 h byte addresses 12 - 15 = 0c h - 0f h this four-byte field is the password required for access to the oe m area of the mic3003?s memory and registers. this field is compared to the four-byte oempw field at serial address a2 h . if the two fields match, access is allowed to the oem areas of the mic3003 non-volatile memory at serial addresses a4 h and a6 h . the oem password may be set by writing the new value into oempwset. the new password will not take effect until after a power-on reset occurs or a warm reset is performed using the rst bit in oemcfg0. this allows the new password to be verified before it takes effect. these registers are non-volatile and will be maintained through po wer and reset cycles. a valid oem password is required for access to this register. byte weight 3 oem password, most significant byte 2 oem password, 2nd most significant byte 1 oem password, 2nd least significant byte 0 oem password, least significant byte oem calibration 0 (oemcal0) d[7] reserved read-only d[6] fltdis read/write d[5] fspin read/write d[4] wrinh read/write d[3] apccal read/write d[2] reserved read-only d[1] reserved read-only d[0] frcops read/write default value 0000 0000 b = 00 h serial address a6 h byte address 16 = 10 h a valid oem password is required for access to this register. this register is volatile and will not keep its value through pow er cycles.
micrel, inc. MIC3003GFL july 2010 62 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 bit function operation d[7] reserved always writ e as zero; reads undefined. d[6] fltdis fault comparator disable 0 = fault comparator faults enabled 1 = fault comparator faults disabled when fltdis is high, the faul t comparator does not run, and the following faults are not detected: ? high ibias faults ? high transmit power faults ? low receive power faults if a fault condition was detected prior to the assertion of fltdis, the fault flag will remain active until cleared, but cannot be set again until the fault comparator is allowed to run. d[5] fspin fault comparator ?spin-on-channel? mode select; do not enable adc and fc spin- on-channel modes simultaneously. 0 = normal fault comparator operation 1 = force the fault comparator to spin on one channel when the fault comparator spins on just one channel (selected via oemcal1[1:0]), the two channels not being examined will not, of course, respond to fault conditions. d[4] wrinh inhibit nvram write cy cles. 0 = normal nvram operation 1 = inhibit nvram writes when wrinh is high, writes to the mic3003?s internal memory do not occur. registers that are non-volatile are written with the new value, but will not retain that value through a power cycle, since the nvram backing storage has not been modified. d[3] apccal selects apc dac calibration mode - dacs may be controlled directly. 0 = normal mode 1 = dac calibration mode. when dac calibration mode is enabled, the temperature compensation lookup tables are disabled, so the dacs are presented with the values written into their corresponding registers. d[2:1] reserved always writ e as zeros; reads undefined. d[0] frcops forces outputs for board-level or system- level testing 0 = normal operation 1 = force outputs for testing: the following outputs are driven to their active states: ? txfault (active polarity set in oemcfg5) ? /int (only driven if the oemim bit is clear in fltmsk) ? rxlos (active polarity and rxlos selection are set in oemcfg6)
micrel, inc. MIC3003GFL july 2010 63 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 oem calibration 1 (oemcal1) d[7] reserved read-only d[6] adstp read/write d[5] adidl read-only d[4] oneshot read/write d[3] adspin read/write d[2] spin[2] read/write d[1] spin[1] read/write d[0] spin[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 17 = 11 h a valid oem password is required for access to this register. this register is volatile and will not keep its value through pow er cycles. bit function operation d[7] reserved always writ e as zero; reads undefined. d[6] adstp stop adc: halts the analog to digital converter 0 = adc in normal operation 1 = adc stopped when adstp is set, the five-channel adc halts and no new adc results are computed. existing result registers are not changed. in addition, no new temperature compensation is applied to the apc loop and fault parameters, and no comparisons of the adc results against the alarm and warning limits is performed. d[5] adidl adc idle flag 0 = adc is busy 1 = adc is idle adidl may be used in conjunction with oneshot to determine when the single adc conversion is complete. after oneshot is set, the adc runs until completion and then halts. software may poll adidl to detect this completion before interrofating the result. d[4] oneshot triggers one-shot a/d conversion cycle 0 = normal adc operation 1 = adc one-shot mode setting oneshot high starts the adc and causes it to stop after the next conversion is complete. after the conversion, the adc remains stopped until oneshot is set low. multiple single adc conversions may be executed by repeatedly writing one to oneshot. d[3] adspin selects adc spin-on-channel mode; do not enable adc and fc spin-on-channel modes simultaneously 0 = normal adc operation 1 = adc spin-on-channel d[2:0] spin[2:0] adc and fault comparator (fc) channel select for spin-on-channel mode; do not enable adc and fc spin-on-channel modes simultaneously adc: 000 = temperature 001 = voltage 010 = vild 011 = vmpd 100 = vrx
micrel, inc. MIC3003GFL july 2010 64 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 lut index (lutindx) d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value (before the first set of 16 temperature measurements has been accumulated) 0000 0000 b = 00 h serial address a6 h byte address 18 = 12h the look-up table index is derived from the cu rrent temperature measurement as follows: index = t avg / 2 where t avg is the current average temperature, aver aged over a set of 16 samples. this register allows the current table index to be read by the host. the appropriate table base address must be added to lutindx to form a complete table index in physical memory. a valid oem password is required for access to this register. oem configuration 3 (oemcfg3) d[7] qgpom read/write d[6] txfpol read/write d[5] gpod read/write d[4] gpom read/write d[3] gpoc read/write d[2] txfinm read/write d[1] losdis read/write d[0] intcal read/write default value 0000 1000 b = 08 h serial address a6 h byte address 19 = 13 h this register is non-volatile and will be maintained through powe r and reset cycles. a valid oem password is required for acces s to this register.
micrel, inc. MIC3003GFL july 2010 65 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 bit function operation d[7] qgpom qgpo pin function select 0: gpo (general purpose output) 1: reset output d[6] txfpol txfin active polarity select; a fault is indicated when txfin = txfpol 0 = the txfin input is active-low 1 = the txfin input is active-high this bit is ignored if txfinm = 0 d[5] gpod gpo output drive 0 = gpo output is open-drain 1 = gpo output is push-pull this bit is ignored if gpom = 0 d[4] gpom gpo/rrsout pin mode select 0 = rrsout output 1 = gpo output d[3] gpoc gpo output control 0 = set the gpo pin low 1 = set the gpo pin high this bit is ignored if gpom = 0 d[2] txfinm shdn/txfin pin mode select 0 = shdn output 1 = txfin input d[1] losdis rxlos comparator and output disable 0 = rxlos fault enabled, and the rxlos output is enabled for normal operation 1 = rxlos fault disabled; also, the rxlos output is disabled, and will remain low d[0] intcal calibration mode select 0 = external calibration mode 1 = internal calibration(the mic3003?s alu applies slope and offset coefficients to t he alu results as necessary) bias dac setting (apcdac) current vbias setting d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value 0000 0000 b = 00 h serial address a6 h byte address 20 = 14 h this register reflects (reads back) the value being sent to the bias dac (apcset0, apcset 1, or apcset2 whichever is selected, with temperature compensation applied). a valid oem password is required for access to this register.
micrel, inc. MIC3003GFL july 2010 66 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 modulation dac setting (moddac) current vmod setting d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value 0000 0000 b = 00 h serial address a6 h byte address 21 = 15 h this register reflects (reads back) the value set in the bein g sent to the modulation dac (mo dset0, modset1, or modset2 whichever is selected, with temperature compensation applied). a valid oem password is required for access to this register. oem readback register (oemrd) d[7] reserved read-only d[6] kill_laser read-only d[5] rxp_flt read-only d[4] int read-only d[3] apcsat read-only d[2] ibflt read-only d[1] txflt read-only d[0] rrsout read-only default value 0000 0000 b = 00 h serial address a6 h byte address 22 = 16 h this register reflects (reads back) the status of the bits corresponding to the parameters defined below. a valid oem password is required for access to this register. bit function operation d[7] reserved always reads as a zero d[6] kill_laser state of the internal laser disable signal 0: the mic3003 is disabling the laser 1: the laser is enabled to operate d[5] rxp_flt registered fault comparator detection of a receive power fault 0: no fault comparator receive power fault 1: the fault comparator has detected a receive power fault d[4] int mirrors state of /int but active- high 1 = the interrupt is asserted 0 = no pending interrupt. d[3] apcsat registered apc saturation fault 1 = apc saturation fault detected 0 = normal operation. d[2] ibflt registered fault comparator detection of an ibias fault 1 = ibias fault detected 0 = normal operation d[1] txflt registered fault comparator detection of a transmit power fault 1 = registered transmit power fault 0 = normal operation d[0] trsout state of the rate select output pin, trsout 1 = high; 0 = low
micrel, inc. MIC3003GFL july 2010 67 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 signal detect threshold (losfltn) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 23 = 17 h this eight-bit register works in conjuncti on with the losflt register to provide hy steresis and control t he operation of the lo ss of signal comparator. the comparator?s output, rxlos, is assert ed when the input on vrx falls below the level in losflt. the output will then be de-asserted when the vrx si gnal rises above the level in losfltn. the input signal is subject to scaling by t he rxpot. if the los comparator is disabled , i.e., losdis = 1, this register is igno red. a valid oem password is required for access to this register. this register is non-volatile and will be maintained through pow er and reset cycles. rx eepot tap selection (rxpot) d[7] reserved read-only d[6] reserved read-only d[5] reserved read-only d[4] rxpot[4] read/write d[3] rxpot[3] read/write d[2] rxpot[2] read/write d[1] rxpot[1] read/write d[0] rxpot[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 24 = 18 h this register is non-volatile and will be maintained through powe r and reset cycles. a valid oem password is required for acces s to these registers. bit(s) function operation d[7:5] reserved reserved. always wr ite as zero; reads return zeros. d[4:0] rxpot t ap selection: adjust gain of the receive power measurement: 00000 = no divider action 00001 = 31/32 00010 = 30/32 ? ? ? 11110 = 2/32 11111 = 1/32 oem configuration 4 (oemcfg4) d[7] txf_wrn read/write d[6] txf_alm read/write d[5] lat_wrn read/write d[4] lat_alm read/write d[3] istart[3] read/write d[2] istart[2] read/write d[1] istart[1] read/write d[0] istart[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 25 = 19 h this register is non-volatile and will be maintained through power and reset cycles. a valid oem password is required for access to these registers.
micrel, inc. MIC3003GFL july 2010 68 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 bit(s) function operation d[7] txf_wrn allows warnings to assert txfault 0: warnings do not assert txfault 1: warnings assert txfault the rxpwr low warning flag does not assert txfault d[6] txf_alm allows alarms to assert txfault 0: alarms do not assert txfault 1: alarms assert txfault the rxpwr low alarm flag does not assert txfault d[5] lat_wrn warning latch 0: warnings flags are latched. they are cleared by reading the register or toggling txdisable. 1: warnings flags are not latched., i.e. they are set and reset with the warning condition. the flags are also cleared by reading the register or toggling txdisable. d[4] lat_alm alarm latch 0: alarms flags are latched. they are cleared by reading the register or toggling txdisable. 1: alarms flags are not latched., i.e. they are set and reset with alarm condition. the flags are also cleared by reading the register or toggling txdisable. d[3:0] istart[3:0] i start current level selection. i start current level selection: 0000 = no i start current 0001 - 1111 = 0.375 ma x i start[ [3:0] i start is used to speed up the laser start-up after a fault occurs. the charging current of the compensation capacitor starts from i start instead of ramping up from 0. oem configuration 5 (oemcfg5) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 26 = 1a h this register is non-volatile and will be maintained through powe r and reset cycles. a valid oem password is required for acces s to these registers.
micrel, inc. MIC3003GFL july 2010 69 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 bit(s) function operation d[7] shdn output enable / disable 0: shdn is enabled. txfault will trigger the shdn output 1: shdn is disabled. txfault has no effect on the shdn output this applies when pin 12 is set as the shdn output d[6] lookup table temperature offset control 0: the temperature result used for the lut access averaging algorithm does not have the offset coefficient applied 1: the temperature result used for the lut access averaging algorithm is offset by the signed 6-bit (.5 c resolution) offset coefficient. d[5] temperature result register offset control 0: the temperature result register does not have the offset coefficient applied 1: the temperature result register is o ffset by the signed 6-bit (.5 c resolution) offset coefficient. d[4] polarity of txfault 0: txfault is active-high 1: txfault is active-low d[3] smbus multipart support 0: multipart mode off 1: multipart mode on d[2] oem password location 0: a6h: 120-123 (78h-7bh) 1: a6h: 123-126 (7bh-7eh) d[1] smbus timeout enable / disable 0: smbus timeout enabled 1: smbus timeout disabled oem configuration 6 (oemcfg6) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 27 = 1b h this register is non-volatile and will be maintained through powe r and reset cycles. a valid oem password is required for acces s to these registers.
micrel, inc. MIC3003GFL july 2010 70 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 bit(s) function operation d[7] a0h space access control 0: a0h space is used according to sff-8472 1: a0h space does not respond to any access request. smbus transactions to a0h receive a nack response. d[6:5] rxpwr linearization intervals 00: temperature-based coefficient selection 01: programmable delimiters 10: hard coded delimiters 11: reserved options 01 and 10 partition the receive power result range into eight regions, each of which has its own slope and offset coefficients. the delimiters identify the region boundaries within the 12-bit receive power range of results, and may be either hard-coded (10) or programmable (01). use of hard-coded delimiters frees up ex tra a6 memory space for scratchpad use. d[4] txdisable debo unce enable / disable 0: txdisable is not debounced 1: txdisable is debounced. glitches less than 5 ms are rejected. set this bit to 1 if a mechanical swit ch is used for txdisable. set to 0 for normal operation to assure compliance to the sfp msa. d[3] rxlos polarity 0: the rxlos output is low for normal op eration and high with a loss of signal condition. 1: the rxlos output is high for norma l operation (signal detected) and low with a loss of signal (no signal detected) condition. d[2] rxlos/trsout select 0: rxlos is selected for output 1: trrsout is selected for output d[1] temperature resolution 0: temperature is measured to a resolu tion of 1 oc (eight-bit resolution) 1: temperature is measured to a resolu tion of 0.5 oc (nine-bit resolution) d[0] txfault clear mode 0: txfault remains set until txdisable is toggled 1: txfault is in continuous mode a nd follows the stat e of the faults in continuous mode, the fault conditions asserting txfault are not registered and turn on and off according to the mic3003?s operation. power-on hour meter data (pohdata) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default values for all bytes when the mic3003 is shipped 0000 0000 b = 00 h serial address a6 h byte addresses 32 ? 34 and 36 - 38 = 20 h - 22 h and 24 h - 26 h these registers are used for backing up the poh result during power cycles. at power-u p, the poh meter selects the larger of the two values as the initial count. incremental results are st ored in alternate register pairs. the power-on hour meter may be reset or preset by writing to these registers. these registers are not typically intended to be used by the oem or end user. the current value of the power-on hours meter may be read from the pohh and pohl registers. if it is necessary to preset the power-on hours meter to a spec ific value, please consult the factory for the exact format to b e written to the pohdata registers. these registers are non-volatile and will be maintained through po wer and reset cycles. a valid oem password is required for access to these registers.
micrel, inc. MIC3003GFL july 2010 71 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 byte weight 3 poha, high-byte 2 poha, low-byte 1 pohb, high-byte 0 pohb, low-byte oem scratchpad registers (scratchn) default value 0000 0000 b = 00 h serial address a6 h byte addresses 136 - 207 (88 - cf h ) 208 - 221 (d0 - dd h ): this area is part of the oe m scratch pad only if the hard- coded delimiters option for receive power linearization is used. 222 - 250 (de - fa h ) the scratchpad registers are general-purpose non-volatile memory lo cations. they can be freely read from and written to any time the mic3003 is in oem mode. rx power coefficient look-up table (rxlutn) default values offset coefficients ar e set to a default value of zero slope coefficients are set to a default value of 1.0 serial address a6 h byte addresses 40 - 71 = 28 h - 47 h these registers hold the receive power slope and offset coeffici ents used to calibrate the mic300 3?s adc receive power result in internal calibration mode. these registers are non-volatile and will be maintained through po wer and reset cycles. a valid oem password is required for access to these registers. a6 address bytes definition 40 (28h) rxslp0h rx slope 0, high byte 41 (29h) rxslp0l rx slope 0, low byte 42 (2ah) rxoff0h rx offset 0, high byte 43 (2bh) rxoff0l rx offset 0, low byte 44 (2ch) rxslp1h rx slope 1, high byte 45 (2dh) rxslp1l rx slope 1, low byte 46 (2eh) rxoff1h rx offset 1, high byte 47 (2fh) rxoff1l rx offset 1, low byte ? ? ? ? ? ? 68 (44h) rxslp7h rx slope 7, high byte 69 (45h) rxslp7l rx slope 7, low byte 70 (46h) rxoff7h rx offset 7, high byte 71 (47h) rxoff7l rx offset 7, low byte
micrel, inc. MIC3003GFL july 2010 72 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 calibration constants (calcoefn) default values offset coefficients ar e set to a default value of zero slope coefficients are set to a default value of 1.0 serial address a6 h byte addresses 74 - 87 = 4ah - 57h these registers hold the slope and offset coefficients used to ca librate the mic3003?s adc results in internal calibration mode . note that the temperature offset is also used in external ca libration mode; but this can be disabled in oemcfg5 (or by setting the offset coefficient to zero). these registers are non-volatile and will be maintained through po wer and reset cycles. a valid oem password is required for access to these registers. a6 address bytes definition 74 (4ah) toffh temperature offset (six -bit signed offset, .5 c resolution) 75 (4bh) toff0l not used 76 (4ch) vslp0h voltage slope, high byte 77 (4dh) vslp0l voltage slope, low byte 78 (4eh) voffh voltage offset, high byte 79 (4fh) voff0l voltage offset, low byte 80 (50h) islp0h bias current slope, high byte 81 (51h) islp0l bias current slope, low byte 82 (52h) ioffh bias current offset, high byte 83 (53h) ioff0l bias curre nt offset, low byte 84 (54h) txslph tx power slope, high byte 85 (55h) txslpl tx power slope, low byte 86 (56h) txoffh tx power offset, high byte 87 (57h) txoffl tx power offset, low byte manufacturer id register (mfg_id) identifies micrel as the manufacturer of the device. always returns 2ah d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only default value 0010 1010 b = 2a h serial address a6 h byte address 254 = fe h the value in this register, in combination with the dev_id regi ster, serves to identify the mic3003 and its revision number to software. this register is read-only. bit(s) function operation d[7:0] identifies micrel as the manufacturer of the device. always returns 2a h . read-only. always returns a h
micrel, inc. MIC3003GFL july 2010 73 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 device id register (dev_id) d[7] read-only d[6] read-only d[5] read-only d[4] read-only d[3] read-only d[2] read-only d[1] read-only d[0] read-only mic3003 device id always reads 0 at d[ 7-6] and 11 at d[5-4] die revision default value 0011 xxxx b = 3x h serial address a6 h byte address 255 = ff h the value in this register, in combination with the mfg_id regi ster, serve to identify the mic3003 and its revision number to software. this register is read-only.
micrel, inc. MIC3003GFL july 2010 74 m9999-072910-a hbwhelp@micrel.com or (408) 955-1690 package information 24-pin mlf ? (mlf-24) micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is belie ved to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authori zed for use as components in life support app liances, devices or systems where malfu nction of a product can reasonably be expected to result in pers onal injury. life support devices or system s are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a si gnificant injury to the user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or systems is a purchaser?s own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2010 micrel , incor p orated.

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